Tanmoy Roy

Person

Greater Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Elements for in-memory compute
- Patent number 11,829,730
- Issue date Nov 28, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density array, in memory computing
- Patent number 11,798,615
- Issue date Oct 24, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory management device, system and method
- Patent number 11,749,343
- Issue date Sep 5, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of comparators within a memory safety logic circuit using a...
- Patent number 11,742,045
- Issue date Aug 29, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Rohit Bhasin
- G11 - INFORMATION STORAGE
Information Patent Grant
In-memory compute array with integrated bias elements
- Patent number 11,605,424
- Issue date Mar 14, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port memory cell with improved access resistance
- Patent number 11,532,633
- Issue date Dec 20, 2022
- STMicroelectronics International N.V.
- Tushar Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Elements for in-memory compute
- Patent number 11,474,788
- Issue date Oct 18, 2022
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory calibration device, system and method
- Patent number 11,398,289
- Issue date Jul 26, 2022
- STMicroelectronics International N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for at speed detection of a word line fault cond...
- Patent number 11,393,532
- Issue date Jul 19, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
High-density array, in memory computing
- Patent number 11,335,397
- Issue date May 17, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory management device, system and method
- Patent number 11,257,543
- Issue date Feb 22, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual port memory cell with improved access resistance
- Patent number 11,152,376
- Issue date Oct 19, 2021
- STMicroelectronics International N.V.
- Tushar Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-memory compute array with integrated bias elements
- Patent number 11,094,376
- Issue date Aug 17, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of comparators within a memory safety logic circuit using a...
- Patent number 10,998,077
- Issue date May 4, 2021
- STMicroelectronics International N.V.
- Rohit Bhasin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for adaptive read-write operation in self-timed...
- Patent number 10,706,915
- Issue date Jul 7, 2020
- STMicroelectronics International N.V.
- Abhishek Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage, master-slave flip-flop
- Patent number 10,637,447
- Issue date Apr 28, 2020
- Alok Kumar Tripathi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for adaptive read-write operation in self-timed...
- Patent number 10,283,191
- Issue date May 7, 2019
- STMicroelectronics International N.V.
- Abhishek Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage, master-slave flip-flop
- Patent number 10,277,207
- Issue date Apr 30, 2019
- STMicroelectronics International N.V.
- Alok Kumar Tripathi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for a pulse generator
- Patent number 9,590,602
- Issue date Mar 7, 2017
- STMicroelectronics International N.V.
- Shishir Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for testing of a memory with redundancy elements
- Patent number 8,458,545
- Issue date Jun 4, 2013
- STMicroelectronics International N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Biased sensing module
- Patent number 7,791,970
- Issue date Sep 7, 2010
- STMicroelectronics Pvt. Ltd.
- Tanmoy Roy
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ELEMENTS FOR IN-MEMORY COMPUTE
- Publication number 20230004354
- Publication date Jan 5, 2023
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH DENSITY ARRAY, IN MEMORY COMPUTING
- Publication number 20220238150
- Publication date Jul 28, 2022
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20220139453
- Publication date May 5, 2022
- STMicroelectronics International N.V.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE
- Publication number 20220020754
- Publication date Jan 20, 2022
- STMicroelectronics International N.V.
- Tushar SHARMA
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS
- Publication number 20210343334
- Publication date Nov 4, 2021
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CALIBRATION DEVICE, SYSTEM AND METHOD
- Publication number 20210233600
- Publication date Jul 29, 2021
- STMicroelectronics International N.V.
- Tanmoy ROY
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...
- Publication number 20210225453
- Publication date Jul 22, 2021
- STMicroelectronics International N.V.
- Rohit BHASIN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPUTING, HIGH-DENSITY ARRAY
- Publication number 20210065776
- Publication date Mar 4, 2021
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20200411089
- Publication date Dec 31, 2020
- STMicroelectronics International N.V.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELEMENTS FOR IN-MEMORY COMPUTE
- Publication number 20200387352
- Publication date Dec 10, 2020
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS
- Publication number 20200388330
- Publication date Dec 10, 2020
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...
- Publication number 20200342940
- Publication date Oct 29, 2020
- STMicroelectronics International N.V.
- Tanmoy ROY
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...
- Publication number 20200219579
- Publication date Jul 9, 2020
- STMicroelectronics International N.V.
- Rohit BHASIN
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED...
- Publication number 20190279707
- Publication date Sep 12, 2019
- STMicroelectronics International N.V.
- Abhishek PATHAK
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE, MASTER-SLAVE FLIP-FLOP
- Publication number 20190273484
- Publication date Sep 5, 2019
- STMicroelectronics International N.V.
- Alok Kumar TRIPATHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE
- Publication number 20190198508
- Publication date Jun 27, 2019
- STMicroelectronics International N.V.
- Tushar SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and Method for a Pulse Generator
- Publication number 20150365080
- Publication date Dec 17, 2015
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AN...
- Publication number 20130058155
- Publication date Mar 7, 2013
- STMICROELECTRONICS PVT. LTD.
- Olivier Callen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS
- Publication number 20120137188
- Publication date May 31, 2012
- STMICROELECTRONICS PVT. LTD.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Application
BIASED SENSING MODULE
- Publication number 20080212354
- Publication date Sep 4, 2008
- STMicroelectronics Pvt. Ltd.
- Tanmoy Roy
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Elements for in-memory compute

High density array, in memory computing

Memory management device, system and method

Testing of comparators within a memory safety logic circuit using a...

In-memory compute array with integrated bias elements

Dual port memory cell with improved access resistance

Elements for in-memory compute

Memory calibration device, system and method

Circuit and method for at speed detection of a word line fault cond...

High-density array, in memory computing

Memory management device, system and method

Dual port memory cell with improved access resistance

In-memory compute array with integrated bias elements

Testing of comparators within a memory safety logic circuit using a...

Method and circuit for adaptive read-write operation in self-timed...

Low voltage, master-slave flip-flop

Method and circuit for adaptive read-write operation in self-timed...

Low voltage, master-slave flip-flop

System and method for a pulse generator

Method and apparatus for testing of a memory with redundancy elements

Biased sensing module

Patents Applicationslast 30 patents

ELEMENTS FOR IN-MEMORY COMPUTE

HIGH DENSITY ARRAY, IN MEMORY COMPUTING

MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS

MEMORY CALIBRATION DEVICE, SYSTEM AND METHOD

TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...

MEMORY COMPUTING, HIGH-DENSITY ARRAY

MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD

ELEMENTS FOR IN-MEMORY COMPUTE

IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS

CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...

TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...

METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED...

LOW VOLTAGE, MASTER-SLAVE FLIP-FLOP

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

System and Method for a Pulse Generator

SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AN...

METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS

BIASED SENSING MODULE