Tatsuo Nakato

Person

Vancouver, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming silicon-germanium/Si/silicon dioxide heterostruc...
- Patent number 5,792,679
- Issue date Aug 11, 1998
- Sharp Microelectronics Technology, Inc.
- Tatsuo Nakato
- B82 - NANO-TECHNOLOGY
Information Patent Grant
GE-SI SOI MOS transistor and method of fabricating same
- Patent number 5,726,459
- Issue date Mar 10, 1998
- Sharp Microelectronics Technology, Inc.
- Sheng Teng Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor with implanted dielectric layer having patched pin-holes
- Patent number 5,608,252
- Issue date Mar 4, 1997
- Sharp Microelectronics Technology, Inc.
- Tatsuo Nakato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of treating silicon to obtain thin, buried insulating layer
- Patent number 5,589,407
- Issue date Dec 31, 1996
- Implanted Material Technology, Inc.
- Narayanan Meyyappan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Graded implantation of oxygen and/or nitrogen constituents to defin...
- Patent number 5,514,897
- Issue date May 7, 1996
- Sharp Microelectronics Technology, Inc.
- Tatsuo Nakato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow SIMOX processing method using molecular ion implantation
- Patent number 5,436,175
- Issue date Jul 25, 1995
- Sharp Microelectronics Technology, Inc.
- Tatsuo Nakato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Graded implantation of oxygen and/or nitrogen constituents to defin...
- Patent number 5,395,771
- Issue date Mar 7, 1995
- Sharp Kabushiki Kaisha
- Tatsuo Nakato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pin-hole patch method for implanted dielectric layer
- Patent number 5,278,077
- Issue date Jan 11, 1994
- Sharp Microelectronics Technology, Inc.
- Tatsuo Nakato
- H01 - BASIC ELECTRIC ELEMENTS

Tatsuo Nakato

Person

Patents Grantslast 30 patents

Method for forming silicon-germanium/Si/silicon dioxide heterostruc...

GE-SI SOI MOS transistor and method of fabricating same

Semiconductor with implanted dielectric layer having patched pin-holes

Method of treating silicon to obtain thin, buried insulating layer

Graded implantation of oxygen and/or nitrogen constituents to defin...

Shallow SIMOX processing method using molecular ion implantation

Graded implantation of oxygen and/or nitrogen constituents to defin...

Pin-hole patch method for implanted dielectric layer