Te-Long Chiu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Segmented bit line EEPROM page architecture
- Patent number 6,621,733
- Issue date Sep 16, 2003
- Turbo IC, Inc.
- Te-Long Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Trench-isolated EEPROM flash in segmented bit line page architecture
- Patent number 6,359,305
- Issue date Mar 19, 2002
- Turbo IC, Inc.
- Te-Long Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for fabricating an EEPROM
- Patent number 6,277,692
- Issue date Aug 21, 2001
- Turbo IC
- Te-Long Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile dynamic random access memory array and the method of f...
- Patent number 5,140,551
- Issue date Aug 18, 1992
- Te-Long Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically-erasable and electrically-programmable memory storage...
- Patent number 5,021,848
- Issue date Jun 4, 1991
- Te-Long Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically-flash-erasable and electrically-programmable memory st...
- Patent number 5,019,879
- Issue date May 28, 1991
- Te-Long Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically alterable non-volatile memory device
- Patent number 4,780,750
- Issue date Oct 25, 1988
- Sierra Semiconductor Corporation
- Joseph G. Nolan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an MOS memory array having electrically-progr...
- Patent number 4,490,900
- Issue date Jan 1, 1985
- Seeq Technology, Inc.
- Te-Long Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chime unit for electric clock and mechanical clock
- Patent number 4,323,995
- Issue date Apr 6, 1982
- Te-Long Chiu
- G04 - HOROLOGY

Patents Applicationslast 30 patents

Information Patent Application
Segmented bit line EEPROM page architecture
- Publication number 20020135013
- Publication date Sep 26, 2002
- Te-Long Chiu
- H01 - BASIC ELECTRIC ELEMENTS

Te-Long Chiu

Person

Patents Grantslast 30 patents

Segmented bit line EEPROM page architecture

Trench-isolated EEPROM flash in segmented bit line page architecture

Process for fabricating an EEPROM

Non-volatile dynamic random access memory array and the method of f...

Electrically-erasable and electrically-programmable memory storage...

Electrically-flash-erasable and electrically-programmable memory st...

Electrically alterable non-volatile memory device

Method of fabricating an MOS memory array having electrically-progr...

Chime unit for electric clock and mechanical clock

Patents Applicationslast 30 patents

Segmented bit line EEPROM page architecture