TED R. WHITE

Person

AUSTIN, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Split-gate non-volatile memory cells having improved overlap tolerance
- Patent number 9,111,908
- Issue date Aug 18, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a shared contact in a semiconductor device
- Patent number 8,426,310
- Issue date Apr 23, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device including a heterojunction region
- Patent number 8,390,026
- Issue date Mar 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Brian A. Winstead
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate non-volatile memory cell having improved overlap toleran...
- Patent number 8,163,615
- Issue date Apr 24, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified hybrid orientation technology
- Patent number 8,125,032
- Issue date Feb 28, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor structure using silicon germanium
- Patent number 7,927,956
- Issue date Apr 19, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Split gate non-volatile memory cell with improved endurance and met...
- Patent number 7,923,769
- Issue date Apr 12, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Split gate non-volatile memory cell with improved endurance and met...
- Patent number 7,923,328
- Issue date Apr 12, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Electronic devices including a semiconductor layer
- Patent number 7,821,067
- Issue date Oct 26, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor structure having a strained sili...
- Patent number 7,811,382
- Issue date Oct 12, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- C30 - CRYSTAL GROWTH
Information Patent Grant
Twisted dual-substrate orientation (DSO) substrates
- Patent number 7,803,670
- Issue date Sep 28, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with asymmetry for data storage circuitry
- Patent number 7,799,644
- Issue date Sep 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure
- Patent number 7,781,840
- Issue date Aug 24, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Step height reduction between SOI and EPI for DSO and BOS integration
- Patent number 7,749,829
- Issue date Jul 6, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Gauri V. Karve
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic devices including a semiconductor layer
- Patent number 7,737,496
- Issue date Jun 15, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
Information Patent Grant
Integrated circuit with different channel materials for P and N cha...
- Patent number 7,700,420
- Issue date Apr 20, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming vertical structures in a semiconductor device
- Patent number 7,556,992
- Issue date Jul 7, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Zhonghai Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench liner for DSO integration
- Patent number 7,544,548
- Issue date Jun 9, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified hybrid orientation technology
- Patent number 7,524,707
- Issue date Apr 28, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor fabrication process using etch stop layer to optimize...
- Patent number 7,494,856
- Issue date Feb 24, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Da Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with stressors and method therefor
- Patent number 7,479,422
- Issue date Jan 20, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Brian A. Winstead
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a multiple crystal orientation semiconductor device
- Patent number 7,402,477
- Issue date Jul 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI active layer with different surface orientation
- Patent number 7,288,458
- Issue date Oct 30, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to selectively form regions having differing properties and...
- Patent number 7,285,452
- Issue date Oct 23, 2007
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a dual strained channel semiconductor device
- Patent number 7,282,402
- Issue date Oct 16, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic devices including a semiconductor layer and a process fo...
- Patent number 7,265,004
- Issue date Sep 4, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Graded semiconductor layer
- Patent number 7,241,647
- Issue date Jul 10, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor fabrication using double etch/refill process
- Patent number 7,226,820
- Issue date Jun 5, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Da Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure and method therefor
- Patent number 7,226,833
- Issue date Jun 5, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Template layer formation
- Patent number 7,208,357
- Issue date Apr 24, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING IMPROVED OVERLAP TOLERANCE
- Publication number 20120241839
- Publication date Sep 27, 2012
- FREESCALE SEMICONDUCTOR, INC.
- TED R. WHITE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE
- Publication number 20110294292
- Publication date Dec 1, 2011
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND MET...
- Publication number 20110031548
- Publication date Feb 10, 2011
- FREESCALE SEMICONDUCTOR, INC.
- TED R. WHITE
- B82 - NANO-TECHNOLOGY
Information Patent Application
SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND MET...
- Publication number 20090256191
- Publication date Oct 15, 2009
- Ted R. White
- B82 - NANO-TECHNOLOGY
Information Patent Application
Modified Hybrid Orientation Technology
- Publication number 20090218625
- Publication date Sep 3, 2009
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Step height reduction between SOI and EPI for DSO and BOS integration
- Publication number 20080274594
- Publication date Nov 6, 2008
- Gauri V. Karve
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE INCLUDING A HETEROJUNCTION REGION AND A PROCESS F...
- Publication number 20080111153
- Publication date May 15, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian A. Winstead
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming vertical structures in a semiconductor device
- Publication number 20080023803
- Publication date Jan 31, 2008
- Freescale Semiconductor, Inc.
- Zhonghai Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY
- Publication number 20080026529
- Publication date Jan 31, 2008
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Twisted Dual-Substrate Orientation (DSO) Substrates
- Publication number 20080020515
- Publication date Jan 24, 2008
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE HAVING A STRAINED SILI...
- Publication number 20070277728
- Publication date Dec 6, 2007
- Mariam G. Sadaka
- C30 - CRYSTAL GROWTH
Information Patent Application
Trench liner for DSO integration
- Publication number 20070281436
- Publication date Dec 6, 2007
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER
- Publication number 20070272952
- Publication date Nov 29, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Transistor Structure and a Method for Making the Same
- Publication number 20070257322
- Publication date Nov 8, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Zhonghai Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with different channel materials for P and N cha...
- Publication number 20070241403
- Publication date Oct 18, 2007
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making a multiple crystal orientation semiconductor device
- Publication number 20070238233
- Publication date Oct 11, 2007
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
- Publication number 20070235807
- Publication date Oct 11, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor fabrication process using etch stop layer to optimize...
- Publication number 20070238250
- Publication date Oct 11, 2007
- Freescale Semiconductor, Inc.
- Da Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with stressors and method therefor
- Publication number 20070210314
- Publication date Sep 13, 2007
- Brian A. Winstead
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to selectively form regions having differing properties and...
- Publication number 20070190745
- Publication date Aug 16, 2007
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI active layer with different surface orientation
- Publication number 20070134891
- Publication date Jun 14, 2007
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic devices including a semiconductor layer and a process fo...
- Publication number 20070108481
- Publication date May 17, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Voon-Yew Thean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM
- Publication number 20070082453
- Publication date Apr 12, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Modified hybrid orientation technology
- Publication number 20070048919
- Publication date Mar 1, 2007
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device featuring an arched structure strained semicon...
- Publication number 20060226492
- Publication date Oct 12, 2006
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making a semiconductor device having an arched structure...
- Publication number 20060228872
- Publication date Oct 12, 2006
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor fabrication using double etch/refill process
- Publication number 20060228842
- Publication date Oct 12, 2006
- Freescale Semiconductor, Inc.
- Da Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making a dual strained channel semiconductor device
- Publication number 20060228851
- Publication date Oct 12, 2006
- Mariam G. Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device structure and method therefor
- Publication number 20060094169
- Publication date May 4, 2006
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS
- Publication number 20060084235
- Publication date Apr 20, 2006
- Freescale Semiconductor, Inc.
- Alexander L. Barr
- H01 - BASIC ELECTRIC ELEMENTS

TED R. WHITE

Person

Patents Grantslast 30 patents

Split-gate non-volatile memory cells having improved overlap tolerance

Method of forming a shared contact in a semiconductor device

Electronic device including a heterojunction region

Split-gate non-volatile memory cell having improved overlap toleran...

Modified hybrid orientation technology

Method for making a semiconductor structure using silicon germanium

Split gate non-volatile memory cell with improved endurance and met...

Split gate non-volatile memory cell with improved endurance and met...

Electronic devices including a semiconductor layer

Method for forming a semiconductor structure having a strained sili...

Twisted dual-substrate orientation (DSO) substrates

Transistor with asymmetry for data storage circuitry

Semiconductor device structure

Step height reduction between SOI and EPI for DSO and BOS integration

Electronic devices including a semiconductor layer

Integrated circuit with different channel materials for P and N cha...

Method for forming vertical structures in a semiconductor device

Trench liner for DSO integration

Modified hybrid orientation technology

Semiconductor fabrication process using etch stop layer to optimize...

Semiconductor device with stressors and method therefor

Method of making a multiple crystal orientation semiconductor device

SOI active layer with different surface orientation

Method to selectively form regions having differing properties and...

Method of making a dual strained channel semiconductor device

Electronic devices including a semiconductor layer and a process fo...

Graded semiconductor layer

Transistor fabrication using double etch/refill process

Semiconductor device structure and method therefor

Template layer formation

Patents Applicationslast 30 patents

SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING IMPROVED OVERLAP TOLERANCE

METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE

SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND MET...

SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND MET...

Modified Hybrid Orientation Technology

Step height reduction between SOI and EPI for DSO and BOS integration

ELECTRONIC DEVICE INCLUDING A HETEROJUNCTION REGION AND A PROCESS F...

Method for forming vertical structures in a semiconductor device

TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY

Twisted Dual-Substrate Orientation (DSO) Substrates

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE HAVING A STRAINED SILI...

Trench liner for DSO integration

ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER

Hybrid Transistor Structure and a Method for Making the Same

Integrated circuit with different channel materials for P and N cha...

Method of making a multiple crystal orientation semiconductor device

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR

Semiconductor fabrication process using etch stop layer to optimize...

Semiconductor device with stressors and method therefor

Method to selectively form regions having differing properties and...

SOI active layer with different surface orientation

Electronic devices including a semiconductor layer and a process fo...

METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM

Modified hybrid orientation technology

Semiconductor device featuring an arched structure strained semicon...

Method of making a semiconductor device having an arched structure...

Transistor fabrication using double etch/refill process

Method of making a dual strained channel semiconductor device

Semiconductor device structure and method therefor

LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS