Thomas E. Tang

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for in-situ doping of deposited silicon
- Patent number 5,198,387
- Issue date Mar 30, 1993
- Texas Instruments Incorporated
- Thomas E. Tang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Silicided structures having openings therein
- Patent number 5,166,770
- Issue date Nov 24, 1992
- Texas Instruments Incorporated
- Thomas E. Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for integrating optical sensor into processor
- Patent number 5,101,764
- Issue date Apr 7, 1992
- Texas Instruments Incorporated
- Lee M. Loewenstein
- G01 - MEASURING TESTING
Information Patent Grant
Vertical LPCVD reactor
- Patent number 5,076,206
- Issue date Dec 31, 1991
- Texas Instruments Incorporated
- Dane E. Bailey
- C30 - CRYSTAL GROWTH
Information Patent Grant
Oxide-isolated source/drain transistor
- Patent number 5,043,778
- Issue date Aug 27, 1991
- Texas Instruments Incorporated
- Clarence W. Teng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making CMOS device with both P+ and N+ gates including...
- Patent number 5,010,032
- Issue date Apr 23, 1991
- Texas Instruments Incorporated
- Thomas E. Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM with local interconnect
- Patent number 4,975,756
- Issue date Dec 4, 1990
- Texas Instruments Incorporated
- Roger A. Haken
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making oxide-isolated source/drain transistor
- Patent number 4,963,502
- Issue date Oct 16, 1990
- Texas Instruments, Incorporated
- Clarence W. Teng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective silicidation process using a titanium nitride protective...
- Patent number 4,920,073
- Issue date Apr 24, 1990
- Texas Instruments, Incorporated
- Che-Chia Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS device with both p+ and n+ gates
- Patent number 4,890,141
- Issue date Dec 26, 1989
- Texas Instruments Incorporated
- Thomas E. Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for etching titanium nitride local interconnects
- Patent number 4,878,994
- Issue date Nov 7, 1989
- Texas Instruments Incorporated
- Rhett B. Jucha
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for formation of shallow silicided junctions
- Patent number 4,788,160
- Issue date Nov 29, 1988
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local interconnect
- Patent number 4,746,219
- Issue date May 24, 1988
- Texas Instruments Incorporated
- Thomas C. Holloway
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide-capped titanium silicide formation
- Patent number 4,690,730
- Issue date Sep 1, 1987
- Texas Instruments Incorporated
- Thomas E. Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to increase tin thickness
- Patent number 4,676,866
- Issue date Jun 30, 1987
- Texas Instruments Incorporated
- Thomas E. Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for patterning local interconnects
- Patent number 4,657,628
- Issue date Apr 14, 1987
- Texas Instruments Incorporated
- Thomas C. Holloway
- H01 - BASIC ELECTRIC ELEMENTS

Thomas E. Tang

Person

Patents Grantslast 30 patents

Method and apparatus for in-situ doping of deposited silicon

Silicided structures having openings therein

Method and apparatus for integrating optical sensor into processor

Vertical LPCVD reactor

Oxide-isolated source/drain transistor

Process for making CMOS device with both P+ and N+ gates including...

SRAM with local interconnect

Method of making oxide-isolated source/drain transistor

Selective silicidation process using a titanium nitride protective...

CMOS device with both p+ and n+ gates

Method for etching titanium nitride local interconnects

Process for formation of shallow silicided junctions

Local interconnect

Oxide-capped titanium silicide formation

Process to increase tin thickness

Process for patterning local interconnects