Thomas G. Sopchak

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pre-test power-optimized bin reassignment following selective volta...
- Patent number 10,295,592
- Issue date May 21, 2019
- Global Foundries Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-test power-optimized bin reassignment following selective volta...
- Patent number 9,759,767
- Issue date Sep 12, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold voltage (VT)-type transistor sensitive and/or fan-out sen...
- Patent number 9,653,330
- Issue date May 16, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic method and apparatus for non-destructively observing lat...
- Patent number 7,916,826
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of adding fabrication monitors to integrated circuit chips
- Patent number 7,620,931
- Issue date Nov 17, 2009
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diagnostic method and apparatus for non-destructively observing lat...
- Patent number 7,453,973
- Issue date Nov 18, 2008
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of adding fabrication monitors to integrated circuit chips
- Patent number 7,323,278
- Issue date Jan 29, 2008
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for defect monitoring of semiconductor devices...
- Patent number 7,285,860
- Issue date Oct 23, 2007
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Grant
Method of adding fabrication monitors to integrated circuit chips
- Patent number 7,240,322
- Issue date Jul 3, 2007
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Utilizing clock shield as defect monitor
- Patent number 7,239,167
- Issue date Jul 3, 2007
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Grant
Designing scan chains with specific parameter sensitivities to iden...
- Patent number 7,194,706
- Issue date Mar 20, 2007
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic method and apparatus for non-destructively observing lat...
- Patent number 7,145,977
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Darren L Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Utilizing clock shield as defect monitor
- Patent number 7,088,124
- Issue date Aug 8, 2006
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Grant
Defect diagnosis for semiconductor integrated circuits
- Patent number 7,089,514
- Issue date Aug 8, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Grant
Method and structure for defect monitoring of semiconductor devices...
- Patent number 7,078,248
- Issue date Jul 18, 2006
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Grant
Utilizing clock shield as defect monitor
- Patent number 7,005,874
- Issue date Feb 28, 2006
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Grant
Diagnosable scan chain
- Patent number 7,007,214
- Issue date Feb 28, 2006
- International Business Machines Corporation
- Steven Michael Eustis
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for monitoring defects
- Patent number 6,998,866
- Issue date Feb 14, 2006
- International Business Machines Corporation
- Greg Bazan
- G01 - MEASURING TESTING
Information Patent Grant
Scan-bypass architecture without additional external latches
- Patent number 5,925,143
- Issue date Jul 20, 1999
- International Business Machines Corporation
- Pamela Sue Gillis
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan-bypass architecture without additional external latches
- Patent number 5,719,879
- Issue date Feb 17, 1998
- International Business Machines Corporation
- Pamela Sue Gillis
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...
- Publication number 20170276726
- Publication date Sep 28, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Application
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...
- Publication number 20160313394
- Publication date Oct 27, 2016
- International Business Machines Corporation
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...
- Publication number 20090180584
- Publication date Jul 16, 2009
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
- Publication number 20080017857
- Publication date Jan 24, 2008
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
- Publication number 20070160920
- Publication date Jul 12, 2007
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UTILIZING CLOCK SHIELD AS DEFECT MONITOR
- Publication number 20070108964
- Publication date May 17, 2007
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Application
Diagnostic Method and Apparatus For Non-Destructively Observing Lat...
- Publication number 20070033458
- Publication date Feb 8, 2007
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
- Publication number 20060225023
- Publication date Oct 5, 2006
- International Business Machines Corporation
- James W. Adkisson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES...
- Publication number 20060170104
- Publication date Aug 3, 2006
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Application
Utilizing clock shield as defect monitor
- Publication number 20060066342
- Publication date Mar 30, 2006
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Application
DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
- Publication number 20060036975
- Publication date Feb 16, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Application
Designing Scan Chains With Specific Parameter Sensitivities to Iden...
- Publication number 20060026472
- Publication date Feb 2, 2006
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHOD FOR MONITORING DEFECTS
- Publication number 20060022693
- Publication date Feb 2, 2006
- International Business Machines Corporation
- Greg Bazan
- G01 - MEASURING TESTING
Information Patent Application
UTILIZING CLOCK SHIELD AS DEFECT MONITOR
- Publication number 20050285611
- Publication date Dec 29, 2005
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES...
- Publication number 20050282297
- Publication date Dec 22, 2005
- International Business Machines Corporation
- John M. Cohn
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...
- Publication number 20050025277
- Publication date Feb 3, 2005
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Application
DIAGNOSABLE SCAN CHAIN
- Publication number 20040268195
- Publication date Dec 30, 2004
- International Business Machines Corporation
- Steven Michael Eustis
- G01 - MEASURING TESTING

Thomas G. Sopchak

Person

Patents Grantslast 30 patents

Pre-test power-optimized bin reassignment following selective volta...

Pre-test power-optimized bin reassignment following selective volta...

Threshold voltage (VT)-type transistor sensitive and/or fan-out sen...

Diagnostic method and apparatus for non-destructively observing lat...

Method of adding fabrication monitors to integrated circuit chips

Diagnostic method and apparatus for non-destructively observing lat...

Method of adding fabrication monitors to integrated circuit chips

Method and structure for defect monitoring of semiconductor devices...

Method of adding fabrication monitors to integrated circuit chips

Utilizing clock shield as defect monitor

Designing scan chains with specific parameter sensitivities to iden...

Diagnostic method and apparatus for non-destructively observing lat...

Utilizing clock shield as defect monitor

Defect diagnosis for semiconductor integrated circuits

Method and structure for defect monitoring of semiconductor devices...

Utilizing clock shield as defect monitor

Diagnosable scan chain

Circuit and method for monitoring defects

Scan-bypass architecture without additional external latches

Scan-bypass architecture without additional external latches

Patents Applicationslast 30 patents

PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...

PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...

DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...

METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS

METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS

UTILIZING CLOCK SHIELD AS DEFECT MONITOR

Diagnostic Method and Apparatus For Non-Destructively Observing Lat...

METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS

METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES...

Utilizing clock shield as defect monitor

DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS

Designing Scan Chains With Specific Parameter Sensitivities to Iden...

CIRCUIT AND METHOD FOR MONITORING DEFECTS

UTILIZING CLOCK SHIELD AS DEFECT MONITOR

METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES...

DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LAT...

DIAGNOSABLE SCAN CHAIN