Thomas J. Massingill

Person

Scotts Valley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Die down semiconductor package
- Patent number 7,489,517
- Issue date Feb 10, 2009
- Thomas Joel Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with recess for die
- Patent number 7,239,024
- Issue date Jul 3, 2007
- Thomas Joel Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip module and method for forming and method for deplating d...
- Patent number 6,882,045
- Issue date Apr 19, 2005
- Thomas J. Massingill
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layer opto-electronic substrates with electrical and optical...
- Patent number 6,845,184
- Issue date Jan 18, 2005
- Fujitsu Limited
- Tetsuzo Yoshimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional opto-electronic modules with electrical and optic...
- Patent number 6,690,845
- Issue date Feb 10, 2004
- Fujitsu Limited
- Tetsuzo Yoshimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Opto-electronic substrates with electrical and optical interconnect...
- Patent number 6,611,635
- Issue date Aug 26, 2003
- Fujitsu Limited
- Tetsuzo Yoshimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Modules with pins and methods for making modules with pins
- Patent number 6,448,106
- Issue date Sep 10, 2002
- Fujitsu Limited
- Wen-chou Vincent Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible pin count package for semiconductor device
- Patent number 6,380,001
- Issue date Apr 30, 2002
- VLSI Technology, Inc.
- Byoung-Youl Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems based on opto-electronic substrates with electrical and opt...
- Patent number 6,343,171
- Issue date Jan 29, 2002
- Fujitsu Limited
- Tetsuzo Yoshimura
- G02 - OPTICS
Information Patent Grant
Method and structure of z-connected laminated substrate for high de...
- Patent number 6,326,555
- Issue date Dec 4, 2001
- Fujitsu Limited
- Mark Thomas McCormack
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor with polymeric layer
- Patent number 6,271,107
- Issue date Aug 7, 2001
- Fujitsu Limited
- Thomas Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer laminated substrates with high density interconnects and...
- Patent number 6,163,957
- Issue date Dec 26, 2000
- Fujitsu Limited
- Hunt Hang Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Production and test socket for ball grid array semiconductor package
- Patent number 5,947,751
- Issue date Sep 7, 1999
- VLSI Technology, Inc.
- Thomas J. Massingill
- G01 - MEASURING TESTING
Information Patent Grant
Bump formation on yielded semiconductor dies
- Patent number 5,587,336
- Issue date Dec 24, 1996
- VLSI Technology
- Tsing-Chow Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photo-definable template for semiconductor chip alignment
- Patent number 5,561,328
- Issue date Oct 1, 1996
- Digital Equipment Corporation
- Thomas J. Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin cavity down ball grid array package based on wirebond technology
- Patent number 5,420,460
- Issue date May 30, 1995
- VLSI Technology, Inc.
- Thomas J. Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photo-definable template for semiconductor chip alignment
- Patent number 5,413,964
- Issue date May 9, 1995
- Digital Equipment Corporation
- Thomas J. Massingill
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Cavity down semiconductor package
- Publication number 20050218514
- Publication date Oct 6, 2005
- Thomas Joel Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with recess for die
- Publication number 20040195699
- Publication date Oct 7, 2004
- Thomas Joel Massingill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-chip module and method for forming and method for deplating d...
- Publication number 20020155661
- Publication date Oct 24, 2002
- Thomas J. Massingill
- H01 - BASIC ELECTRIC ELEMENTS

Thomas J. Massingill

Person

Patents Grantslast 30 patents

Die down semiconductor package

Semiconductor package with recess for die

Multi-chip module and method for forming and method for deplating d...

Multi-layer opto-electronic substrates with electrical and optical...

Three-dimensional opto-electronic modules with electrical and optic...

Opto-electronic substrates with electrical and optical interconnect...

Modules with pins and methods for making modules with pins

Flexible pin count package for semiconductor device

Systems based on opto-electronic substrates with electrical and opt...

Method and structure of z-connected laminated substrate for high de...

Semiconductor with polymeric layer

Multilayer laminated substrates with high density interconnects and...

Production and test socket for ball grid array semiconductor package

Bump formation on yielded semiconductor dies

Photo-definable template for semiconductor chip alignment

Thin cavity down ball grid array package based on wirebond technology

Photo-definable template for semiconductor chip alignment

Patents Applicationslast 30 patents

Cavity down semiconductor package

Semiconductor package with recess for die

Multi-chip module and method for forming and method for deplating d...