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Thomas J. Schaefer
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Cupertino, CA, US
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last 30 patents
Information
Patent Grant
Automated optimization of hierarchical netlists
Patent number
5,956,257
Issue date
Sep 21, 1999
VLSI Technology, Inc.
Arnold Ginetti
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for verifying signal timing of electrical circ...
Patent number
5,841,672
Issue date
Nov 24, 1998
VLSI Technology, Inc.
Athanasius W. Spyrou
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Enhanced dynamic programming method for technology mapping of combi...
Patent number
5,787,010
Issue date
Jul 28, 1998
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method for estimating interconnect delays in integrated circuits
Patent number
5,617,325
Issue date
Apr 1, 1997
VLSI Technology, Inc.
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Buffer circuit design using back track searching of site trees
Patent number
5,402,356
Issue date
Mar 28, 1995
VLSI Technology, Inc.
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for synthesizing logic circuits with timing const...
Patent number
5,402,357
Issue date
Mar 28, 1995
VLSI Technology, Inc.
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for setting capacitive constraints on synthesized...
Patent number
5,197,015
Issue date
Mar 23, 1993
VLSI Technology, Inc.
Mark R. Hartoog
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Event-controlled LCC stimulation
Patent number
5,068,812
Issue date
Nov 26, 1991
VLSI Technology, Inc.
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Levelized logic simulator with fenced evaluation
Patent number
5,062,067
Issue date
Oct 29, 1991
VLSI Technology, Inc.
Thomas J. Schaefer
G06 - COMPUTING CALCULATING COUNTING