Thomas Nirschl

Person

Loiching, DE, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit arrangement comprising a field effect transistor...
- Patent number 8,629,500
- Issue date Jan 14, 2014
- Infineon Technologies AG
- Juergen Holz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory using tunneling field effect transistors
- Patent number 8,389,973
- Issue date Mar 5, 2013
- Qimonda AG
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of operating phase-change memory
- Patent number 8,125,821
- Issue date Feb 28, 2012
- Infineon Technologies AG
- Jan Otterstedt
- G11 - INFORMATION STORAGE
Information Patent Grant
Fuse sensing scheme
- Patent number 7,986,024
- Issue date Jul 26, 2011
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory using tunneling field effect transistors
- Patent number 7,880,160
- Issue date Feb 1, 2011
- Qimonda AG
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data retention monitor
- Patent number 7,864,565
- Issue date Jan 4, 2011
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit arrangement for activating a circuit block and method for t...
- Patent number 7,757,109
- Issue date Jul 13, 2010
- Infineon Technologies AG
- Jörg Berthold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-bit resistive memory
- Patent number 7,692,949
- Issue date Apr 6, 2010
- Qimonda North America Corp.
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a drive circuit
- Patent number 7,679,963
- Issue date Mar 16, 2010
- Infineon Technologies AG
- Ronald Kakoschke
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory including two access devices per phase change element
- Patent number 7,652,914
- Issue date Jan 26, 2010
- Qimonda North America Corp.
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Conditioning operations for memory cells
- Patent number 7,646,625
- Issue date Jan 12, 2010
- Qimonda AG
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with trigger element
- Patent number 7,619,917
- Issue date Nov 17, 2009
- Qimonda North America Corp.
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell, read device for memory cell, memory assembly, and corr...
- Patent number 7,606,107
- Issue date Oct 20, 2009
- Infineon Technologies AG
- Peter Huber
- G11 - INFORMATION STORAGE
Information Patent Grant
Device with damaged breakdown layer
- Patent number 7,582,546
- Issue date Sep 1, 2009
- Infineon Technologies AG
- Ronald Kakoschke
- G11 - INFORMATION STORAGE
Information Patent Grant
Readout of multi-level storage cells
- Patent number 7,580,297
- Issue date Aug 25, 2009
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory including write circuit for providing multiple reset pulses
- Patent number 7,577,023
- Issue date Aug 18, 2009
- Qimonda North America Corp.
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Grant
Quasi-differential read operation
- Patent number 7,570,507
- Issue date Aug 4, 2009
- Infineon Technologies North America Corp.
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory having shunted memory cells
- Patent number 7,551,476
- Issue date Jun 23, 2009
- Qimonda North America Corp.
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit including logic portion and memory portion
- Patent number 7,545,019
- Issue date Jun 9, 2009
- Qimonda North America Corp.
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory cell having a sidewall contact
- Patent number 7,541,609
- Issue date Jun 2, 2009
- International Business Machines Corporation
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory cell and corresponding method of producing same
- Patent number 7,531,420
- Issue date May 12, 2009
- Infineon Technologies AG
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Current compliant sensing architecture for multilevel phase change...
- Patent number 7,515,461
- Issue date Apr 7, 2009
- Macronix International Co., Ltd.
- Thomas D. Happ
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit including resistivity changing material element
- Patent number 7,474,555
- Issue date Jan 6, 2009
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory including bipolar transistor access devices
- Patent number 7,436,695
- Issue date Oct 14, 2008
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for switching on a voltage supply of a semicon...
- Patent number 7,427,882
- Issue date Sep 23, 2008
- Infineon Technologies AG
- Stephan Henzler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory having storage locations within a common volume of phase cha...
- Patent number 7,345,899
- Issue date Mar 18, 2008
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
ROM memory cell having defined bit line voltages
- Patent number 7,327,593
- Issue date Feb 5, 2008
- Infineon Technologies AG
- Martin Ostermayr
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS
- Publication number 20110089392
- Publication date Apr 21, 2011
- QIMONDA AG
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Arrangement Comprising a Field Effect Transistor...
- Publication number 20090101975
- Publication date Apr 23, 2009
- INFINEON TECHNOLOGIES AG
- Juergen Holz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA RETENTION MONITOR
- Publication number 20090034343
- Publication date Feb 5, 2009
- INFINEON TECHNOLOGIES AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION
- Publication number 20090027943
- Publication date Jan 29, 2009
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
FUSE SENSING SCHEME
- Publication number 20090002119
- Publication date Jan 1, 2009
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
QUASI-DIFFERENTIAL READ OPERATION
- Publication number 20090003033
- Publication date Jan 1, 2009
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
CONDITIONING OPERATIONS FOR MEMORY CELLS
- Publication number 20090003035
- Publication date Jan 1, 2009
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
- Publication number 20080315171
- Publication date Dec 25, 2008
- Thomas Happ
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION
- Publication number 20080304311
- Publication date Dec 11, 2008
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF OPERATING PHASE-CHANGE MEMORY
- Publication number 20080298121
- Publication date Dec 4, 2008
- Jan Otterstedt
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES
- Publication number 20080273371
- Publication date Nov 6, 2008
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE DIODE MEMORY
- Publication number 20080272354
- Publication date Nov 6, 2008
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FO...
- Publication number 20080247216
- Publication date Oct 9, 2008
- Mark C. H. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PC...
- Publication number 20080247218
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Mark C. H. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Application
Device With Damaged Breakdown Layer
- Publication number 20080246016
- Publication date Oct 9, 2008
- Ronald Kakoschke
- G11 - INFORMATION STORAGE
Information Patent Application
Readout of multi-level storage cells
- Publication number 20080239833
- Publication date Oct 2, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Current Compliant Sensing Architecture for Multilevel Phase Change...
- Publication number 20080165570
- Publication date Jul 10, 2008
- Macronix International Co., Ltd.
- Thomas D. Happ
- G11 - INFORMATION STORAGE
Information Patent Application
Memory including two access devices per phase change element
- Publication number 20080165573
- Publication date Jul 10, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Memory that limits power consumption
- Publication number 20080137401
- Publication date Jun 12, 2008
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Application
Memory cell with trigger element
- Publication number 20080123398
- Publication date May 29, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive memory including bipolar transistor access devices
- Publication number 20080117667
- Publication date May 22, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Phase change memory cell having a sidewall contact
- Publication number 20080116442
- Publication date May 22, 2008
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Combined read/write circuit for memory
- Publication number 20080101110
- Publication date May 1, 2008
- Thomas Happ
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive memory having shunted memory cells
- Publication number 20080080228
- Publication date Apr 3, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive memory having shunted memory cells
- Publication number 20080068878
- Publication date Mar 20, 2008
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Having a Drive Circuit
- Publication number 20080068895
- Publication date Mar 20, 2008
- INFINEON TECHNOLOGIES AG
- Ronald Kakoschke
- G11 - INFORMATION STORAGE
Information Patent Application
High density memory array for low power application
- Publication number 20070279962
- Publication date Dec 6, 2007
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
Memory using tunneling field effect transistors
- Publication number 20070267619
- Publication date Nov 22, 2007
- Thomas Nirschl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory having storage locations within a common volume of phase cha...
- Publication number 20070247898
- Publication date Oct 25, 2007
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Application
High density memory array for low power application
- Publication number 20070217318
- Publication date Sep 20, 2007
- Thomas Nirschl
- G11 - INFORMATION STORAGE

Thomas Nirschl

Person

Patents Grantslast 30 patents

Integrated circuit arrangement comprising a field effect transistor...

Memory using tunneling field effect transistors

Method of operating phase-change memory

Fuse sensing scheme

Memory using tunneling field effect transistors

Data retention monitor

Circuit arrangement for activating a circuit block and method for t...

Multi-bit resistive memory

Integrated circuit having a drive circuit

Memory including two access devices per phase change element

Conditioning operations for memory cells

Memory cell with trigger element

Memory cell, read device for memory cell, memory assembly, and corr...

Device with damaged breakdown layer

Readout of multi-level storage cells

Memory including write circuit for providing multiple reset pulses

Quasi-differential read operation

Resistive memory having shunted memory cells

Integrated circuit including logic portion and memory portion

Phase change memory cell having a sidewall contact

Semiconductor memory cell and corresponding method of producing same

Current compliant sensing architecture for multilevel phase change...

Integrated circuit including resistivity changing material element

Resistive memory including bipolar transistor access devices

Method and apparatus for switching on a voltage supply of a semicon...

Memory having storage locations within a common volume of phase cha...

ROM memory cell having defined bit line voltages

Patents Applicationslast 30 patents

MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS

Integrated Circuit Arrangement Comprising a Field Effect Transistor...

DATA RETENTION MONITOR

RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION

FUSE SENSING SCHEME

QUASI-DIFFERENTIAL READ OPERATION

CONDITIONING OPERATIONS FOR MEMORY CELLS

INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE

INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION

METHOD OF OPERATING PHASE-CHANGE MEMORY

MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES

PHASE CHANGE DIODE MEMORY

METHOD AND APPARATUS FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FO...

DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PC...

Device With Damaged Breakdown Layer

Readout of multi-level storage cells

Current Compliant Sensing Architecture for Multilevel Phase Change...

Memory including two access devices per phase change element

Memory that limits power consumption

Memory cell with trigger element

Resistive memory including bipolar transistor access devices

Phase change memory cell having a sidewall contact

Combined read/write circuit for memory

Resistive memory having shunted memory cells

Resistive memory having shunted memory cells

Integrated Circuit Having a Drive Circuit

High density memory array for low power application

Memory using tunneling field effect transistors

Memory having storage locations within a common volume of phase cha...

High density memory array for low power application