Patent Application
20080068878
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Phase change memory cells 104 are shunted by shunt resistors 116. During a read operation of a phase change memory cell 104, if the memory cell is in a crystalline state, more current flows through the memory cell than through the shunt resistor. If the memory cell is in an amorphous state, more current flows through the shunt resistor than through the memory cell. Sense circuit 118 senses the state of the memory cell based on the current through the shunt resistor. In this way, the time for sense circuit 118 to sense the state of a memory cell 104 is reduced in comparison to a memory array that does not include shunt resistors 116.
As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.
Each phase change memory cell 104 is electrically coupled to a word line 110, a bit line 112, and common or ground 114. For example, phase change memory cell 104a is electrically coupled to bit line 112a, word line 110a, and common or ground 114, and phase change memory cell 104b is electrically coupled to bit line 112a, word line 110b, and common or ground 114. Phase change memory cell 104c is electrically coupled to bit line 112b, word line 110a, and common or ground 114, and phase change memory cell 104d is electrically coupled to bit line 112b, word line 110b, and common or ground 114. Each bit line 112 is electrically coupled to a shunt resistor 116 and sense circuit 118. Each shunt resistor 116 is also electrically coupled to common or ground 114.
Each phase change memory cell 104 includes a phase change element 106 and a transistor 108. While transistor 108 is a field-effect transistor (FET) in the illustrated embodiment, in other embodiments, transistor 108 can be other suitable devices such as a bipolar transistor or a 3D transistor structure. In other embodiments, a diode-like structure may be used in place of transistor 108. Phase change memory cell 104a includes phase change element 106a and transistor 108a. One side of phase change element 106a is electrically coupled to bit line 112a, and the other side of phase change element 106a is electrically coupled to one side of the source-drain path of transistor 108a. The other side of the source-drain path of transistor 108a is electrically coupled to common or ground 114. The gate of transistor 108a is electrically coupled to word line 110a.
Phase change memory cell 104b includes phase change element 106b and transistor 108b. One side of phase change element 106b is electrically coupled to bit line 112a, and the other side of phase change element 106b is electrically coupled to one side of the source-drain path of transistor 108b. The other side of the source-drain path of transistor 108b is electrically coupled to common or ground 114. The gate of transistor 108b is electrically coupled to word line
Phase change memory cell 104c includes phase change element 106c and transistor 108c. One side of phase change element 106c is electrically coupled to bit line 112b, and the other side of phase change element 106c is electrically coupled to one side of the source-drain path of transistor 108c. The other side of the source-drain path of transistor 108c is electrically coupled to common or ground 114. The gate of transistor 108c is electrically coupled to word line 110a.
Phase change memory cell 104d includes phase change element 106d and transistor 108d. One side of phase change element 106d is electrically coupled to bit line 112b, and the other side of phase change element 106d is electrically coupled to one side of the source-drain path of transistor 108d. The other side of the source-drain path of transistor 108d is electrically coupled to common or ground 114. The gate of transistor 108d is electrically coupled to word line 110b.
In another embodiment, each phase change element 106 is electrically coupled to common or ground 114 and each transistor 108 is electrically coupled to a bit line 112. For example, for phase change memory cell 104a, one side of phase change element 106a is electrically coupled to common or ground 114. The other side of phase change element 106a is electrically coupled to one side of the source-drain path of transistor 108a. The other side of the source-drain path of transistor 108a is electrically coupled to bit line 112a.
Each phase change element 106 comprises a phase change material that may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase change material of phase change element 106 is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.
Shunt resistor 116a shunts current from memory cells 104a-104d on bit line 112a, and shunt resistor 116b shunts current from memory cells 104c-104d on bit line 112b. In one embodiment, resistors 116a-116b are linear resistors. In another embodiment, resistors 116a-116b are active devices configured to act as resistors. During a read operation of a selected memory cell 104, more current flows through the selected memory cell 104 than the shunt resistor 116 if the memory cell is in a lower resistance crystalline state. More current, however, flows through the shunt resistor 116 than through the selected memory cell 104 if the selected memory cell 104 is in a higher resistance amorphous state. The resistance values of shunt resistors 116 are selected to be between the lower resistance of the crystalline state and the higher resistance of the amorphous state.
Sense circuit 118 reads the states of memory cells 104a-104d through bit lines 112a-112b based on the current through shunt resistors 116a-116b. In one embodiment, to read the resistance of one of the memory cells 104a-104d sense circuit 118 provides current that flows through one of the memory cells 104a-104d and one of shunt resistors 116a-116b through bit lines 112a-112b and sense circuit 118 reads the voltage across that one of the memory cells 106a-106b and shunt resistors 116a-116b. With a selected memory cell 104a-104d in a crystalline state, sense circuit 118 senses a lower voltage than with the selected memory cell in an amorphous state.
During a set operation of phase change memory cell 104a, a set current or voltage pulse is selectively enabled and sent through bit line 112a to phase change element 106a thereby heating it above its crystallization temperature (but usually below its melting temperature) with word line 110a selected to activate transistor 108a. In this way, phase change element 106a reaches its crystalline state during this set operation. During a reset operation of phase change memory cell 104a, a reset current or voltage pulse is selectively enabled and sent through bit line 112a to phase change element 106a. The reset current or voltage quickly heats phase change element 106a above its melting temperature. After the current or voltage pulse is turned off, the phase change element 106a quickly quench cools into the amorphous state. Phase change memory cells 104b-104d and other phase change memory cells 104 in memory array 100 are set and reset similarly to phase change memory cell 104a using a similar current or voltage pulse.
Optional switch 124 is a transmission gate, transistor, or other suitable switch. Switch 124 is turned on to couple bit line 112a to shunt resistor 116a to pass signals between bit line 112a and shunt resistor 116a. Switch 124 is turned off to block signals from passing between bit line 112a and shunt resistor 1116a. In one embodiment, optional switch 124 is part of sense circuit 118. In one embodiment, the bit line quench device acts as a shunt device by controlling the resistance of the quench device to an appropriate value.
Sense amplifier 118a receives the REF signal on REF signal path 120 and the signal on bit line 112a to provide the OUT signal on OUT signal path 122. In response to the signal on bit line 112a having a value greater than the REF signal, sense amplifier 118a outputs a logic high OUT signal on OUT signal path 122. In response to the signal on bit line 112a having a value less than the REF signal, sense amplifier 118a output a logic low OUT signal on OUT signal path 122. In other embodiments, the logic levels of the OUT signal on OUT signal path 122 are reversed.
During a read operation and with switch 124 turned on, a current is applied to bit line 112a and a memory cell 104a-104b is selected. The current is divided between the selected memory cell and shunt resistor 116a based on the state of the phase change element within the selected memory cell. Sense amplifier 118a compares the REF signal to the signal on bit line 112a to provide the OUT signal indicating the state of the selected memory cell. In one embodiment, if the voltage across shunt resistor 116a is greater than a voltage on REF signal path 120, sense amplifier 118a outputs a logic high signal on OUT signal path 122 indicating the selected memory cell is in an amorphous state. In response to the voltage across shunt resistor 116a being less than the voltage on REF signal path 120, sense amplifier 118a outputs a logic low signal on OUT signal path 122 indicating the selected memory cell is in a crystalline state. By shunting the current from memory cells 104a-104b, shunt resistor 116a increases the speed of read operations.
Embodiments of the present invention provide an array of phase change memory cells including shunt resistors. The shunt resistors are centralized to bit lines or inputs of the sense amplifiers. Hence the memory cells are not altered and each memory cell has the same parallel resistance to simplify the read operation.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
