Thomas Roehr

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing memory failures in integrated circuits
- Patent number 7,187,602
- Issue date Mar 6, 2007
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device comprising transition detecting circuit and me...
- Patent number 7,127,598
- Issue date Oct 24, 2006
- Kabushiki Kaisha Toshiba
- Kohei Oikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliable ferro fuse cell
- Patent number 7,102,908
- Issue date Sep 5, 2006
- Infineon Technologies AG
- Roehr Thomas
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing the read signal in ferroelectric memories
- Patent number 6,972,983
- Issue date Dec 6, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing effects of noise coupling in integrated circuits with memo...
- Patent number 6,920,059
- Issue date Jul 19, 2005
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid fuses for redundancy
- Patent number 6,906,969
- Issue date Jun 14, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing of memory integrated circuits
- Patent number 6,903,959
- Issue date Jun 7, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing test circuit
- Patent number 6,885,597
- Issue date Apr 26, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy in series grouped memory architecture
- Patent number 6,856,560
- Issue date Feb 15, 2005
- Infineon Technologies Aktiengesellschaft
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Grant
2T2C signal margin test mode using a defined charge and discharge o...
- Patent number 6,826,099
- Issue date Nov 30, 2004
- Infineon Technologies AG
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM configuration
- Patent number 6,791,871
- Issue date Sep 14, 2004
- Infineon Technologies AG
- Martin Freitag
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated magnetoresistive semiconductor memory configuration
- Patent number 6,775,182
- Issue date Aug 10, 2004
- Infineon Technologies AG
- Thomas Boehm
- G11 - INFORMATION STORAGE
Information Patent Grant
2T2C signal margin test mode using resistive element
- Patent number 6,731,554
- Issue date May 4, 2004
- Infineon Technologies AG
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with memory cell groups
- Patent number 6,724,026
- Issue date Apr 20, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 6,707,736
- Issue date Mar 16, 2004
- Kabushiki Kaisha Toshiba
- Tadashi Miyakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible redundancy for memories
- Patent number 6,687,171
- Issue date Feb 3, 2004
- Infineon Technologies Aktiengesellschaft
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture
- Patent number 6,639,824
- Issue date Oct 28, 2003
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory integrated circuit with improved reliability
- Patent number 6,584,009
- Issue date Jun 24, 2003
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Signal margin test mode for FeRAM with ferroelectric reference capa...
- Publication number 20050063213
- Publication date Mar 24, 2005
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Reliable ferro fuse cell
- Publication number 20050047189
- Publication date Mar 3, 2005
- Roehr Thomas
- G11 - INFORMATION STORAGE
Information Patent Application
High density flash memory with high speed cache data interface
- Publication number 20050050261
- Publication date Mar 3, 2005
- Thomas Roehr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device comprising transition detecting circuit and me...
- Publication number 20040123085
- Publication date Jun 24, 2004
- Kohei Oikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing effects of noise coupling in integrated circuits with memo...
- Publication number 20040105293
- Publication date Jun 3, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C Signal margin test mode using a defined charge and discharge o...
- Publication number 20040095819
- Publication date May 20, 2004
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT
- Publication number 20040095820
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C signal margin test mode using different pre-charge levels for...
- Publication number 20040095799
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory architecture
- Publication number 20040095798
- Publication date May 20, 2004
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Application
Increasing the read signal in ferroelectric memories
- Publication number 20040076031
- Publication date Apr 22, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Hybrid fuses for redundancy
- Publication number 20040057293
- Publication date Mar 25, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS
- Publication number 20040056286
- Publication date Mar 25, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
SENSING OF MEMORY INTEGRATED CIRCUITS
- Publication number 20040057275
- Publication date Mar 25, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Sensing test circuit
- Publication number 20040047171
- Publication date Mar 11, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM configuration
- Publication number 20040017706
- Publication date Jan 29, 2004
- Martin Freitag
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated magnetoresistive semiconductor memory configuration
- Publication number 20040013022
- Publication date Jan 22, 2004
- Thomas Boehm
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20030227806
- Publication date Dec 11, 2003
- Tadashi Miyakawa
- G11 - INFORMATION STORAGE
Information Patent Application
FLEXIBLE REDUNDANCY FOR MEMORIES
- Publication number 20030202387
- Publication date Oct 30, 2003
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy in chained memory architectures
- Publication number 20030202386
- Publication date Oct 30, 2003
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing Memory Failures in Integrated Circuits
- Publication number 20030179616
- Publication date Sep 25, 2003
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING

Thomas Roehr

Person

Patents Grantslast 30 patents

Reducing memory failures in integrated circuits

Semiconductor device comprising transition detecting circuit and me...

Reliable ferro fuse cell

Increasing the read signal in ferroelectric memories

Reducing effects of noise coupling in integrated circuits with memo...

Hybrid fuses for redundancy

Sensing of memory integrated circuits

Sensing test circuit

Redundancy in series grouped memory architecture

2T2C signal margin test mode using a defined charge and discharge o...

MRAM configuration

Integrated magnetoresistive semiconductor memory configuration

2T2C signal margin test mode using resistive element

Memory architecture with memory cell groups

Semiconductor memory device

Flexible redundancy for memories

Memory architecture

Memory integrated circuit with improved reliability

Patents Applicationslast 30 patents

Signal margin test mode for FeRAM with ferroelectric reference capa...

Reliable ferro fuse cell

High density flash memory with high speed cache data interface

Semiconductor device comprising transition detecting circuit and me...

Reducing effects of noise coupling in integrated circuits with memo...

2T2C Signal margin test mode using a defined charge and discharge o...

2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT

2T2C signal margin test mode using different pre-charge levels for...

Ferroelectric memory architecture

Increasing the read signal in ferroelectric memories

Hybrid fuses for redundancy

MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS

SENSING OF MEMORY INTEGRATED CIRCUITS

Sensing test circuit

MRAM configuration

Integrated magnetoresistive semiconductor memory configuration

SEMICONDUCTOR MEMORY DEVICE

FLEXIBLE REDUNDANCY FOR MEMORIES

Redundancy in chained memory architectures

Reducing Memory Failures in Integrated Circuits