Thomas W. S. Thomson

Person

Santa Cruz, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for reducing taken branch penalty
- Patent number 6,735,689
- Issue date May 11, 2004
- Raza Microelectronics, Inc.
- Thomas W. S. Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit searching through 8, 16, or 32 bit operands using a 32 bit data...
- Patent number 5,831,877
- Issue date Nov 3, 1998
- National Semiconductor Corporation
- Thomas William Schaw Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double precision (64 bit) shift operations using a 32 bit data path
- Patent number 5,687,102
- Issue date Nov 11, 1997
- National Semiconductor Corp.
- Thomas William Schaw Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution unit architecture to support X86 instruction set and X86...
- Patent number 5,655,139
- Issue date Aug 5, 1997
- National Semiconductor Corporation
- Thomas William Schaw Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Barrel shifter
- Patent number 5,652,718
- Issue date Jul 29, 1997
- National Semiconductor Corporation
- Thomas William Schaw Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined multiplier and accumulator
- Patent number 5,442,579
- Issue date Aug 15, 1995
- National Semiconductor Corporation
- Thomas W. S. Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signed overflow sticky bits
- Patent number 5,319,588
- Issue date Jun 7, 1994
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CPU with integrated multiply/accumulate unit
- Patent number 5,311,458
- Issue date May 10, 1994
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout efficient 32-bit shifter/register with 16-bit interface
- Patent number 5,218,564
- Issue date Jun 8, 1993
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING

Thomas W. S. Thomson

Person

Patents Grantslast 30 patents

Method and system for reducing taken branch penalty

Bit searching through 8, 16, or 32 bit operands using a 32 bit data...

Double precision (64 bit) shift operations using a 32 bit data path

Execution unit architecture to support X86 instruction set and X86...

Barrel shifter

Combined multiplier and accumulator

Signed overflow sticky bits

CPU with integrated multiply/accumulate unit

Layout efficient 32-bit shifter/register with 16-bit interface