Tien Duc Pham

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 9,654,123
- Issue date May 16, 2017
- Altera Corporation
- Tien Duc Pham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 9,350,530
- Issue date May 24, 2016
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated optical-electronic interface in programmable integrated...
- Patent number 9,002,155
- Issue date Apr 7, 2015
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for generating fractional periodic signals
- Patent number 8,995,599
- Issue date Mar 31, 2015
- Altera Corporation
- Tien Duc Pham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,866,520
- Issue date Oct 21, 2014
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-purpose phase-locked loop for low cost transceiver
- Patent number 8,619,931
- Issue date Dec 31, 2013
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,542,042
- Issue date Sep 24, 2013
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for generating fractional periodic signals
- Patent number 8,537,956
- Issue date Sep 17, 2013
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-phase interpolators and related methods
- Patent number 8,294,500
- Issue date Oct 23, 2012
- Altera Corporation
- Vinh Van Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase-locked loop architecture and clock distribution system
- Patent number 8,228,102
- Issue date Jul 24, 2012
- Altera Corporation
- Tien Duc Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for phase interpolation
- Patent number 7,994,837
- Issue date Aug 9, 2011
- Altera Corporation
- Vinh Van Ho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Carry circuit with power-save mode
- Patent number 7,436,208
- Issue date Oct 14, 2008
- Xilinx, Inc.
- Tien Duc Pham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic block with carry chains providing lookahead func...
- Patent number 7,268,587
- Issue date Sep 11, 2007
- Xilinx, Inc.
- Tien Pham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic block providing carry chain with programmable in...
- Patent number 7,256,612
- Issue date Aug 14, 2007
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EYE DIAGRAM CAPTURE TEST DURING PRODUCTION
- Publication number 20210270888
- Publication date Sep 2, 2021
- Justin TREON
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED...
- Publication number 20120251116
- Publication date Oct 4, 2012
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System for convolutional echo cancellation by iterative autocorrela...
- Publication number 20020191779
- Publication date Dec 19, 2002
- Tien Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System for convolutional echo cancellation by iterative autocorrela...
- Publication number 20020181699
- Publication date Dec 5, 2002
- Tien Pham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Tien Duc Pham

Person

Patents Grantslast 30 patents

Phase-locked loop architecture and clock distribution system

Phase-locked loop architecture and clock distribution system

Integrated optical-electronic interface in programmable integrated...

Techniques for generating fractional periodic signals

Phase-locked loop architecture and clock distribution system

Multi-purpose phase-locked loop for low cost transceiver

Phase-locked loop architecture and clock distribution system

Techniques for generating fractional periodic signals

Multi-phase interpolators and related methods

Phase-locked loop architecture and clock distribution system

Techniques for phase interpolation

Carry circuit with power-save mode

Programmable logic block with carry chains providing lookahead func...

Programmable logic block providing carry chain with programmable in...

Patents Applicationslast 30 patents

EYE DIAGRAM CAPTURE TEST DURING PRODUCTION

INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED...

System for convolutional echo cancellation by iterative autocorrela...

System for convolutional echo cancellation by iterative autocorrela...