Tin H. Lai

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock and data recovery circuitry with auto-speed negotiation and o...
- Patent number 8,829,958
- Issue date Sep 9, 2014
- Altera Corporation
- Kazi Asaduzzaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock and data recovery circuitry with auto-speed negotiation and o...
- Patent number 8,811,555
- Issue date Aug 19, 2014
- Altera Corporation
- Kazi Asaduzzaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for decision feedback equalization that reduce variation...
- Patent number 8,416,898
- Issue date Apr 9, 2013
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital adaptation circuitry and methods for programmable logic dev...
- Patent number 8,208,523
- Issue date Jun 26, 2012
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable adaptation convergence detection
- Patent number 8,208,528
- Issue date Jun 26, 2012
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive equalization using data level detection
- Patent number 8,175,143
- Issue date May 8, 2012
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for standby voltage offset cancellation
- Patent number 8,098,087
- Issue date Jan 17, 2012
- Altera Corporation
- John Dung-Ngoc Lam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Equalization circuitry including a digital-to-analog converter havi...
- Patent number 8,063,807
- Issue date Nov 22, 2011
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital adaptation circuitry and methods for programmable logic dev...
- Patent number 7,920,621
- Issue date Apr 5, 2011
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal offset cancellation
- Patent number 7,898,313
- Issue date Mar 1, 2011
- Altera Corporation
- Tin H. Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Half-rate DFE with duplicate path for high data-rate operation
- Patent number 7,782,935
- Issue date Aug 24, 2010
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable digital equalization control circuitry and methods
- Patent number 7,760,799
- Issue date Jul 20, 2010
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal adjustment receiver circuitry
- Patent number 7,733,982
- Issue date Jun 8, 2010
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal adjustment receiver circuitry
- Patent number 7,733,997
- Issue date Jun 8, 2010
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal offset cancellation
- Patent number 7,710,180
- Issue date May 4, 2010
- Altera Corporation
- Tin H. Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Signal adjustment receiver circuitry
- Patent number 7,590,174
- Issue date Sep 15, 2009
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Comparator offset cancellation assisted by PLD resources
- Patent number 7,541,857
- Issue date Jun 2, 2009
- Altera Corporation
- Wilson Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
H-tree driver circuitry
- Patent number 7,514,968
- Issue date Apr 7, 2009
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic bias circuit
- Patent number 7,414,559
- Issue date Aug 19, 2008
- Altera Corporation
- Tin Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal offset cancellation
- Patent number 7,368,968
- Issue date May 6, 2008
- Altera Corporation
- Tin H. Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic bias circuit
- Patent number 7,358,883
- Issue date Apr 15, 2008
- Altera Corporation
- Tin H. Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistance compensated DAC ladder
- Patent number 7,336,211
- Issue date Feb 26, 2008
- Altera Corporation
- Tin H. Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic bias circuit
- Patent number 7,324,031
- Issue date Jan 29, 2008
- Altera Corporation
- Tin Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded memory blocks for programmable logic
- Patent number 6,593,772
- Issue date Jul 15, 2003
- Altera Corporation
- Tony Ngai
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded memory blocks for programmable logic
- Patent number 6,486,702
- Issue date Nov 26, 2002
- Altera Corporation
- Tony Ngai
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND O...
- Publication number 20130093482
- Publication date Apr 18, 2013
- Altera Corporation
- Kazi Asaduzzaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEV...
- Publication number 20110188564
- Publication date Aug 4, 2011
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND O...
- Publication number 20110188621
- Publication date Aug 4, 2011
- Kazi Asaduzzaman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SIGNAL ADJUSTMENT RECEIVER CIRCUITRY
- Publication number 20090285275
- Publication date Nov 19, 2009
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SIGNAL ADJUSTMENT RECEIVER CIRCUITRY
- Publication number 20090284292
- Publication date Nov 19, 2009
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital adaptation circuitry and methods for programmable logic dev...
- Publication number 20080069276
- Publication date Mar 20, 2008
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC BIAS CIRCUIT
- Publication number 20070188353
- Publication date Aug 16, 2007
- Tin Lai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Signal adjustment receiver circuitry
- Publication number 20070147478
- Publication date Jun 28, 2007
- Altera Corporation
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Signal adjustment receiver circuitry
- Publication number 20070140387
- Publication date Jun 21, 2007
- Altera Corporation
- Wilson Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable digital equalization control circuitry and methods
- Publication number 20070071084
- Publication date Mar 29, 2007
- Tin H. Lai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Embedded memory blocks for programmable logic
- Publication number 20020153922
- Publication date Oct 24, 2002
- Altera Corporation
- Tony Ngai
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Clock and data recovery circuitry with auto-speed negotiation and o...

Clock and data recovery circuitry with auto-speed negotiation and o...

Techniques for decision feedback equalization that reduce variation...

Digital adaptation circuitry and methods for programmable logic dev...

Programmable adaptation convergence detection

Adaptive equalization using data level detection

Method and apparatus for standby voltage offset cancellation

Equalization circuitry including a digital-to-analog converter havi...

Digital adaptation circuitry and methods for programmable logic dev...

Signal offset cancellation

Half-rate DFE with duplicate path for high data-rate operation

Programmable digital equalization control circuitry and methods

Signal adjustment receiver circuitry

Signal adjustment receiver circuitry

Signal offset cancellation

Signal adjustment receiver circuitry

Comparator offset cancellation assisted by PLD resources

H-tree driver circuitry

Dynamic bias circuit

Signal offset cancellation

Dynamic bias circuit

Resistance compensated DAC ladder

Dynamic bias circuit

Embedded memory blocks for programmable logic

Embedded memory blocks for programmable logic

Patents Applicationslast 30 patents

CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND O...

DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEV...

CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND O...

SIGNAL ADJUSTMENT RECEIVER CIRCUITRY

SIGNAL ADJUSTMENT RECEIVER CIRCUITRY

Digital adaptation circuitry and methods for programmable logic dev...

DYNAMIC BIAS CIRCUIT

Signal adjustment receiver circuitry

Signal adjustment receiver circuitry

Programmable digital equalization control circuitry and methods

Embedded memory blocks for programmable logic