Torsten Partsch

Person

Chapel Hill, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Maintaining internal voltages of an integrated circuit in response...
- Patent number 7,345,931
- Issue date Mar 18, 2008
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for adjusting threshold drift over temperature i...
- Patent number 7,289,374
- Issue date Oct 30, 2007
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having off-chip driver enable circuit and method for...
- Patent number 7,224,623
- Issue date May 29, 2007
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling clocked standby mode based on device temperature
- Patent number 7,177,219
- Issue date Feb 13, 2007
- Infineon Technologies AG
- David Herbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing adjustable latency for test mode...
- Patent number 7,139,943
- Issue date Nov 21, 2006
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for implementing a power down in a memory device
- Patent number 7,079,441
- Issue date Jul 18, 2006
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with post-amble data strobe signal noise rejec...
- Patent number 7,031,205
- Issue date Apr 18, 2006
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of self-repairing dynamic random access memory
- Patent number 7,028,234
- Issue date Apr 11, 2006
- Infineon Technologies AG
- Jennifer F. Huckaby
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop
- Patent number 7,016,452
- Issue date Mar 21, 2006
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-die detection of the system operation frequency in a DRAM to adj...
- Patent number 6,985,400
- Issue date Jan 10, 2006
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with optional inaccessible memory cells
- Patent number 6,956,786
- Issue date Oct 18, 2005
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for on-die detection of the system operation frequency in a...
- Patent number 6,952,378
- Issue date Oct 4, 2005
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Use of an on-die temperature sensing scheme for thermal protection...
- Patent number 6,873,509
- Issue date Mar 29, 2005
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for temperature throttling the access frequenc...
- Patent number 6,847,911
- Issue date Jan 25, 2005
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G01 - MEASURING TESTING
Information Patent Grant
Use of DQ pins on a ram memory chip for a temperature sensing protocol
- Patent number 6,809,914
- Issue date Oct 26, 2004
- Infineon Technologies AG
- Johnathan T. Edmonds
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating a controllable output voltage
- Patent number 6,784,650
- Issue date Aug 31, 2004
- Infienon Technologies AG
- Thomas Hein
- G05 - CONTROLLING REGULATING
Information Patent Grant
Delay lock loop having an edge detector and fixed delay
- Patent number 6,777,990
- Issue date Aug 17, 2004
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DQS postamble noise suppression by forcing a minimum pulse length
- Patent number 6,760,261
- Issue date Jul 6, 2004
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Indication of the system operation frequency to a DRAM during power-up
- Patent number 6,711,091
- Issue date Mar 23, 2004
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop compensating for effective loads of off-chip driv...
- Patent number 6,696,872
- Issue date Feb 24, 2004
- Infineon Technologies AG
- Thoai-Thai Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having a test operating mode and method for test...
- Patent number 6,670,802
- Issue date Dec 30, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop for generating complementary clock signals
- Patent number 6,661,265
- Issue date Dec 9, 2003
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Current mirror circuit
- Patent number 6,657,422
- Issue date Dec 2, 2003
- Infineon Technologies AG
- Patrick Heyne
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for a delay lock loop
- Patent number 6,653,875
- Issue date Nov 25, 2003
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory having a delay locked loop
- Patent number 6,584,021
- Issue date Jun 24, 2003
- Infineon Technologies AG
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage pump with switch-on control
- Patent number 6,542,389
- Issue date Apr 1, 2003
- Infineon Technology AG
- Stefan Dietrich
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Integrated memory having a row access controller for activating and...
- Patent number 6,532,188
- Issue date Mar 11, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for programming a delay in a signal path
- Patent number 6,480,024
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit configuration for generating an output clock signal with op...
- Patent number 6,366,527
- Issue date Apr 2, 2002
- Infineon Technologies AG
- Thomas Hein
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Circuit and method for adjusting threshold drift over temperature i...
- Publication number 20070223288
- Publication date Sep 27, 2007
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Maintaining internal voltages of an integrated circuit in response...
- Publication number 20070025163
- Publication date Feb 1, 2007
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE
- Publication number 20070019489
- Publication date Jan 25, 2007
- David Herbert
- G11 - INFORMATION STORAGE
Information Patent Application
Method of increasing data setup and hold margin in case of non-symm...
- Publication number 20060215467
- Publication date Sep 28, 2006
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device having off-chip driver enable circuit and method for...
- Publication number 20060203564
- Publication date Sep 14, 2006
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE
- Publication number 20060176751
- Publication date Aug 10, 2006
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory with post-amble data strobe signal noise rejec...
- Publication number 20060168470
- Publication date Jul 27, 2006
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for adjusting threshold drift over temperature i...
- Publication number 20060003715
- Publication date Jan 5, 2006
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory with optional inaccessible memory cells
- Publication number 20050122822
- Publication date Jun 9, 2005
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
On-die detection of the system operation frequency in a DRAM to adj...
- Publication number 20050122832
- Publication date Jun 9, 2005
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory with optional column address strobe latency of...
- Publication number 20050102476
- Publication date May 12, 2005
- Infineon Technologies North America Corp.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Random access memory with post-amble data strobe signal noise rejec...
- Publication number 20050068810
- Publication date Mar 31, 2005
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Application
Method of self-repairing dynamic random access memory
- Publication number 20040064767
- Publication date Apr 1, 2004
- Infineon Technologies North America Corp.
- Jennifer F. Huckaby
- G11 - INFORMATION STORAGE
Information Patent Application
INDICATION OF THE SYSTEM OPERATION FREQUENCY TO A DRAM DURING POWER-UP
- Publication number 20040062136
- Publication date Apr 1, 2004
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
On-die detection of the system operation frequency in a DRAM to adj...
- Publication number 20040062138
- Publication date Apr 1, 2004
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
DQS postamble noise suppression by forcing a minimum pulse length
- Publication number 20040056697
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Shielding line system for an integrated circuit
- Publication number 20040051166
- Publication date Mar 18, 2004
- Guenter Gerstmeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for temperature throttling the access frequenc...
- Publication number 20040024561
- Publication date Feb 5, 2004
- Jennifer Faye Huckaby
- G05 - CONTROLLING REGULATING
Information Patent Application
Combined command set
- Publication number 20030217223
- Publication date Nov 20, 2003
- Infineon Technologies North America Corp.
- Leonel R. Nino
- G11 - INFORMATION STORAGE
Information Patent Application
Use of an on-die temperature sensing scheme for thermal protection...
- Publication number 20030210505
- Publication date Nov 13, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Use of DQ pins on a ram memory chip for a temperature sensing protocol
- Publication number 20030210506
- Publication date Nov 13, 2003
- Johnathan T. Edmonds
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for generating a controllable output voltage
- Publication number 20030205992
- Publication date Nov 6, 2003
- Thomas Hein
- G05 - CONTROLLING REGULATING
Information Patent Application
Method and apparatus for providing adjustable latency for test mode...
- Publication number 20030188238
- Publication date Oct 2, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Delay lock loop having an edge detector and fixed delay
- Publication number 20030179025
- Publication date Sep 25, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR A DELAY LOCK LOOP
- Publication number 20030169085
- Publication date Sep 11, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop
- Publication number 20030012322
- Publication date Jan 16, 2003
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop for generating complementary clock signals
- Publication number 20030001636
- Publication date Jan 2, 2003
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated memory having a row access controller for activating and...
- Publication number 20020141279
- Publication date Oct 3, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a test operating mode and method for test...
- Publication number 20020133750
- Publication date Sep 19, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory having a delay locked loop
- Publication number 20020093855
- Publication date Jul 18, 2002
- Patrick Heyne
- G11 - INFORMATION STORAGE

Torsten Partsch

Person

Patents Grantslast 30 patents

Maintaining internal voltages of an integrated circuit in response...

Circuit and method for adjusting threshold drift over temperature i...

Memory device having off-chip driver enable circuit and method for...

Disabling clocked standby mode based on device temperature

Method and apparatus for providing adjustable latency for test mode...

Methods and apparatus for implementing a power down in a memory device

Random access memory with post-amble data strobe signal noise rejec...

Method of self-repairing dynamic random access memory

Delay locked loop

On-die detection of the system operation frequency in a DRAM to adj...

Random access memory with optional inaccessible memory cells

Method for on-die detection of the system operation frequency in a...

Use of an on-die temperature sensing scheme for thermal protection...

Method and apparatus for temperature throttling the access frequenc...

Use of DQ pins on a ram memory chip for a temperature sensing protocol

Circuit configuration for generating a controllable output voltage

Delay lock loop having an edge detector and fixed delay

DQS postamble noise suppression by forcing a minimum pulse length

Indication of the system operation frequency to a DRAM during power-up

Delay locked loop compensating for effective loads of off-chip driv...

Integrated circuit having a test operating mode and method for test...

Delay locked loop for generating complementary clock signals

Current mirror circuit

Method and apparatus for a delay lock loop

Semiconductor memory having a delay locked loop

Voltage pump with switch-on control

Integrated memory having a row access controller for activating and...

Circuit configuration for programming a delay in a signal path

Circuit configuration for generating an output clock signal with op...

Patents Applicationslast 30 patents

Circuit and method for adjusting threshold drift over temperature i...

Maintaining internal voltages of an integrated circuit in response...

DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE

Method of increasing data setup and hold margin in case of non-symm...

Memory device having off-chip driver enable circuit and method for...

METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE

Random access memory with post-amble data strobe signal noise rejec...

Circuit and method for adjusting threshold drift over temperature i...

Random access memory with optional inaccessible memory cells

On-die detection of the system operation frequency in a DRAM to adj...

Random access memory with optional column address strobe latency of...

Random access memory with post-amble data strobe signal noise rejec...

Method of self-repairing dynamic random access memory

INDICATION OF THE SYSTEM OPERATION FREQUENCY TO A DRAM DURING POWER-UP

On-die detection of the system operation frequency in a DRAM to adj...

DQS postamble noise suppression by forcing a minimum pulse length

Shielding line system for an integrated circuit

Method and apparatus for temperature throttling the access frequenc...

Combined command set

Use of an on-die temperature sensing scheme for thermal protection...

Use of DQ pins on a ram memory chip for a temperature sensing protocol

Circuit configuration for generating a controllable output voltage

Method and apparatus for providing adjustable latency for test mode...

Delay lock loop having an edge detector and fixed delay

METHOD AND APPARATUS FOR A DELAY LOCK LOOP

Delay locked loop

Delay locked loop for generating complementary clock signals

Integrated memory having a row access controller for activating and...

Integrated circuit having a test operating mode and method for test...

Semiconductor memory having a delay locked loop