Uday Mitra

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for controllable metal and barrier-liner recess
- Patent number 11,705,366
- Issue date Jul 18, 2023
- Micromaterials LLC
- He Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned via
- Patent number 11,437,274
- Issue date Sep 6, 2022
- Micromaterials LLC
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of etching metal oxides with less etch residue
- Patent number 11,232,955
- Issue date Jan 25, 2022
- Applied Materials, Inc.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM capacitor module
- Patent number 11,164,938
- Issue date Nov 2, 2021
- Micromaterials LLC
- Uday Mitra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for controllable metal and barrier-liner recess
- Patent number 11,062,942
- Issue date Jul 13, 2021
- Micromaterials LLC
- He Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective removal process to create high aspect ratio fully self-al...
- Patent number 11,037,825
- Issue date Jun 15, 2021
- Micromaterials LLC
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating a fully self-aligned via
- Patent number 10,892,187
- Issue date Jan 12, 2021
- Micromaterials LLC
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for removing metal oxides
- Patent number 10,892,183
- Issue date Jan 12, 2021
- Micromaterials LLC
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective removal process to create high aspect ratio fully self-al...
- Patent number 10,790,191
- Issue date Sep 29, 2020
- Micromaterials LLC
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating a fully self-aligned via
- Patent number 10,699,953
- Issue date Jun 30, 2020
- Micromaterials LLC
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of etching metal oxides with less etch residue
- Patent number 10,622,221
- Issue date Apr 14, 2020
- Applied Materials, Inc.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing self-aligned vias
- Patent number 10,600,688
- Issue date Mar 24, 2020
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectively etched self-aligned via processes
- Patent number 10,593,594
- Issue date Mar 17, 2020
- Micromaterials LLC
- Yung-Chen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing self-aligned grown via
- Patent number 10,573,555
- Issue date Feb 25, 2020
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing fully self-aligned vias and contacts
- Patent number 10,553,485
- Issue date Feb 4, 2020
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned via
- Patent number 10,522,404
- Issue date Dec 31, 2019
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing self-aligned vias
- Patent number 10,510,602
- Issue date Dec 17, 2019
- Mirocmaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned via
- Patent number 10,424,507
- Issue date Sep 24, 2019
- Mirocmaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned via
- Patent number 10,410,921
- Issue date Sep 10, 2019
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned multiple spacer patterning schemes for advanced nanome...
- Patent number 9,978,596
- Issue date May 22, 2018
- Applied Materials, Inc.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned multiple spacer patterning schemes for advanced nanome...
- Patent number 9,548,201
- Issue date Jan 17, 2017
- Applied Materials, Inc.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device having a lanthanum-fa...
- Patent number 8,101,525
- Issue date Jan 24, 2012
- Applied Materials, Inc.
- Meihua Shen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED WET CLEAN FOR EPITAXIAL GROWTH
- Publication number 20230008695
- Publication date Jan 12, 2023
- Applied Materials, Inc.
- Brian K. Kirkpatrick
- B08 - CLEANING
Information Patent Application
FULLY SELF-ALIGNED VIA
- Publication number 20220359289
- Publication date Nov 10, 2022
- Micromaterials LLC.
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM Capacitor Module
- Publication number 20220013624
- Publication date Jan 13, 2022
- Micromaterials LLC.
- Uday Mitra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods For Controllable Metal And Barrier-Liner Recess
- Publication number 20210305091
- Publication date Sep 30, 2021
- Micromaterials LLC.
- He Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Self-Aligned Via
- Publication number 20210090952
- Publication date Mar 25, 2021
- Micromaterials LLC.
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selective Removal Process To Create High Aspect Ratio Fully Self-Al...
- Publication number 20200388535
- Publication date Dec 10, 2020
- Micromaterials LLC.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM Capacitor Module
- Publication number 20200312953
- Publication date Oct 1, 2020
- Micromaterials LLC.
- Uday Mitra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods Of Etching Metal Oxides With Less Etch Residue
- Publication number 20200227275
- Publication date Jul 16, 2020
- Applied Materials, Inc.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULLY SELF-ALIGNED VIA
- Publication number 20200098633
- Publication date Mar 26, 2020
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Creating A Fully Self-Aligned Via
- Publication number 20190378756
- Publication date Dec 12, 2019
- Micromaterials LLC.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Creating A Fully Self-Aligned Via
- Publication number 20190355620
- Publication date Nov 21, 2019
- Micromaterials LLC.
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Self-Aligned Via
- Publication number 20190348323
- Publication date Nov 14, 2019
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selective Removal Process To Create High Aspect Ratio Fully Self-Al...
- Publication number 20190348322
- Publication date Nov 14, 2019
- Micromaterials LLC.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Removing Metal Oxides
- Publication number 20190273019
- Publication date Sep 5, 2019
- Micromaterials LLC.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF ETCHING A TUNGSTEN LAYER
- Publication number 20190198392
- Publication date Jun 27, 2019
- AMRITA B. MULLICK
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Methods For Controllable Metal And Barrier-Liner Recess
- Publication number 20190198389
- Publication date Jun 27, 2019
- Micromaterials LLC.
- He Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selectively Etched Self-Aligned Via Processes
- Publication number 20190189510
- Publication date Jun 20, 2019
- Micromaterials LLC.
- Yung-Chen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods Of Etching Metal Oxides With Less Etch Residue
- Publication number 20190189456
- Publication date Jun 20, 2019
- Applied Materials, Inc.
- Amrita B. Mullick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Self-Aligned Via
- Publication number 20190189512
- Publication date Jun 20, 2019
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods Of Producing Self-Aligned Vias
- Publication number 20190074219
- Publication date Mar 7, 2019
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods Of Producing Self-Aligned Vias
- Publication number 20190067102
- Publication date Feb 28, 2019
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF PRODUCING SELF-ALIGNED GROWN VIA
- Publication number 20190067103
- Publication date Feb 28, 2019
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods Of Producing Fully Self-Aligned Vias And Contacts
- Publication number 20180374750
- Publication date Dec 27, 2018
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Self-Aligned Via
- Publication number 20180286749
- Publication date Oct 4, 2018
- Micromaterials LLC.
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOME...
- Publication number 20170092494
- Publication date Mar 30, 2017
- Applied Materials, Inc.
- Ying ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOME...
- Publication number 20150371852
- Publication date Dec 24, 2015
- Applied Materials, Inc.
- Ying ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FA...
- Publication number 20100210112
- Publication date Aug 19, 2010
- Applied Materials, Inc.
- Meihua Shen
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Methods for controllable metal and barrier-liner recess

Fully self-aligned via

Methods of etching metal oxides with less etch residue

DRAM capacitor module

Methods for controllable metal and barrier-liner recess

Selective removal process to create high aspect ratio fully self-al...

Method for creating a fully self-aligned via

Methods for removing metal oxides

Selective removal process to create high aspect ratio fully self-al...

Method for creating a fully self-aligned via

Methods of etching metal oxides with less etch residue

Methods of producing self-aligned vias

Selectively etched self-aligned via processes

Methods of producing self-aligned grown via

Methods of producing fully self-aligned vias and contacts

Fully self-aligned via

Methods of producing self-aligned vias

Fully self-aligned via

Fully self-aligned via

Self-aligned multiple spacer patterning schemes for advanced nanome...

Self-aligned multiple spacer patterning schemes for advanced nanome...

Method for fabricating a semiconductor device having a lanthanum-fa...

Patents Applicationslast 30 patents

INTEGRATED WET CLEAN FOR EPITAXIAL GROWTH

FULLY SELF-ALIGNED VIA

DRAM Capacitor Module

Methods For Controllable Metal And Barrier-Liner Recess

Fully Self-Aligned Via

Selective Removal Process To Create High Aspect Ratio Fully Self-Al...

DRAM Capacitor Module

Methods Of Etching Metal Oxides With Less Etch Residue

FULLY SELF-ALIGNED VIA

Method For Creating A Fully Self-Aligned Via

Method For Creating A Fully Self-Aligned Via

Fully Self-Aligned Via

Selective Removal Process To Create High Aspect Ratio Fully Self-Al...

Methods for Removing Metal Oxides

METHODS OF ETCHING A TUNGSTEN LAYER

Methods For Controllable Metal And Barrier-Liner Recess

Selectively Etched Self-Aligned Via Processes

Methods Of Etching Metal Oxides With Less Etch Residue

Fully Self-Aligned Via

Methods Of Producing Self-Aligned Vias

Methods Of Producing Self-Aligned Vias

METHODS OF PRODUCING SELF-ALIGNED GROWN VIA

Methods Of Producing Fully Self-Aligned Vias And Contacts

Fully Self-Aligned Via

SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOME...

SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOME...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FA...