Usha Raghuram

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pillar devices and methods of making thereof
- Patent number 8,987,119
- Issue date Mar 24, 2015
- Sandisk 3D LLC
- Vance Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning of submicron pillars in a memory array
- Patent number 8,759,176
- Issue date Jun 24, 2014
- Sandisk 3D LLC
- Usha Raghuram
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Methods for protecting patterned features during trench etch
- Patent number 8,722,518
- Issue date May 13, 2014
- Sandisk 3D LLC
- Steven J. Radigan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene with amorphous carbon for 3D deep via/trench applica...
- Patent number 8,298,931
- Issue date Oct 30, 2012
- Sandisk 3D LLC
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diode array and method of making thereof
- Patent number 8,268,678
- Issue date Sep 18, 2012
- Sandisk 3D LLC
- Steven Maxwell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making a nonvolatile phase change memory cell having a re...
- Patent number 8,163,593
- Issue date Apr 24, 2012
- SanDisk Corporation
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified DARC stack for resist patterning
- Patent number 8,084,366
- Issue date Dec 27, 2011
- Sandisk 3D LLC
- Michael Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Liner for tungsten/silicon dioxide interface in memory
- Patent number 8,071,475
- Issue date Dec 6, 2011
- Sandisk 3D LLC
- Yoichiro Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dielectric overetch using a dielectric etch sto...
- Patent number 8,008,187
- Issue date Aug 30, 2011
- Sandisk 3D LLC
- Samuel V Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of plasma etching transition metal oxides
- Patent number 7,955,515
- Issue date Jun 7, 2011
- Sandisk 3D LLC
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming doped polysilicon via connecting polysilicon layers
- Patent number 7,915,164
- Issue date Mar 29, 2011
- Sandisk 3D LLC
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming doped polysilicon via connecting polysilicon layers
- Patent number 7,915,163
- Issue date Mar 29, 2011
- Sandisk 3D LLC
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pillar devices and methods of making thereof
- Patent number 7,906,392
- Issue date Mar 15, 2011
- Sandisk 3D LLC
- Vance Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diode array and method of making thereof
- Patent number 7,846,782
- Issue date Dec 7, 2010
- Sandisk 3D LLC
- Steven Maxwell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing dielectric overetch using a dielectric etch sto...
- Patent number 7,790,607
- Issue date Sep 7, 2010
- Sandisk 3D LLC
- Samuel V Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile phase change memory cell having a reduced contact area
- Patent number 7,728,318
- Issue date Jun 1, 2010
- SanDisk Corporation
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive hard mask to protect patterned features during trench etch
- Patent number 7,575,984
- Issue date Aug 18, 2009
- Sandisk 3D LLC
- Steven J Radigan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doped polysilicon via connecting polysilicon layers
- Patent number 7,566,974
- Issue date Jul 28, 2009
- SanDisk 3D, LLC
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning submicron pillars
- Patent number 7,517,796
- Issue date Apr 14, 2009
- Sandisk 3D LLC
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dielectric overetch using a dielectric etch sto...
- Patent number 7,422,985
- Issue date Sep 9, 2008
- Sandisk 3D LLC
- Samuel V Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonselective unpatterned etchback to expose buried patterned features
- Patent number 7,307,013
- Issue date Dec 11, 2007
- Sandisk 3D LLC
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for etching and/or patterning a silicon-containing layer
- Patent number 6,890,860
- Issue date May 10, 2005
- Cypress Semiconductor Corporation
- Tinghao F. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming contact openings
- Patent number 6,756,315
- Issue date Jun 29, 2004
- Cypress Semiconductor Corporation
- Hanna Bamnolker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching method
- Patent number 6,406,640
- Issue date Jun 18, 2002
- Cypress Semiconductor Corporation
- Chan-lon Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching method
- Patent number 6,165,375
- Issue date Dec 26, 2000
- Cypress Semiconductor Corporation
- Chan-lon Yang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR PROTECTING PATTERNED FEATURES DURING TRENCH ETCH
- Publication number 20130244395
- Publication date Sep 19, 2013
- SanDisk 3D LLC
- Steven J. Radigan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STO...
- Publication number 20110306177
- Publication date Dec 15, 2011
- Samuel V. Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PILLAR DEVICES AND METHODS OF MAKING THEREOF
- Publication number 20110136326
- Publication date Jun 9, 2011
- SanDisk 3D LLC
- Vance DUNTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diode Array and Method of Making Thereof
- Publication number 20110065243
- Publication date Mar 17, 2011
- SanDisk 3D LLC
- Steven Maxwell
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
- Publication number 20110021019
- Publication date Jan 27, 2011
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STO...
- Publication number 20100297834
- Publication date Nov 25, 2010
- Samuel V. Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH
- Publication number 20090273022
- Publication date Nov 5, 2009
- SanDisk 3D LLC
- Steven J. Radigan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
- Publication number 20090258462
- Publication date Oct 15, 2009
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Modified darc stack for resist patterning
- Publication number 20090258495
- Publication date Oct 15, 2009
- SANDISK 3D LLC
- Michael Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNING OF SUBMICRON PILLARS IN A MEMORY ARRAY
- Publication number 20090224244
- Publication date Sep 10, 2009
- SanDisk 3D LLC
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pillar devices and methods of making thereof
- Publication number 20090179310
- Publication date Jul 16, 2009
- SANDISK 3D LLC
- Vance Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICA...
- Publication number 20090087979
- Publication date Apr 2, 2009
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIODE ARRAY AND METHOD OF MAKING THEREOF
- Publication number 20090085153
- Publication date Apr 2, 2009
- SANDISK 3D LLC
- Steven Maxwell
- G11 - INFORMATION STORAGE
Information Patent Application
LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY
- Publication number 20090085087
- Publication date Apr 2, 2009
- SANDISK CORPORATION
- Yoichiro Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing dielectric overetch using a dielectric etch sto...
- Publication number 20080254615
- Publication date Oct 16, 2008
- Samuel V. Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED CONTACT AREA
- Publication number 20080116441
- Publication date May 22, 2008
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A RE...
- Publication number 20080119007
- Publication date May 22, 2008
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive hard mask to protect patterned features during trench etch
- Publication number 20070284656
- Publication date Dec 13, 2007
- SanDisk 3D LLC
- Steven J. Radigan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of plasma etching transition metals and their compounds
- Publication number 20070010100
- Publication date Jan 11, 2007
- Matrix Semiconductor, Inc.
- Usha Raghuram
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method for reducing dielectric overetch using a dielectric etch sto...
- Publication number 20060216937
- Publication date Sep 28, 2006
- Matrix Semiconductor, Inc.
- Samuel V. Dunton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for patterning submicron pillars
- Publication number 20060183282
- Publication date Aug 17, 2006
- Matrix Semiconductor, Inc.
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Doped polysilicon via connecting polysilicon layers
- Publication number 20060071074
- Publication date Apr 6, 2006
- Matrix Semiconductor, Inc.
- Michael W. Konevecki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nonselective unpatterned etchback to expose buried patterned features
- Publication number 20060003586
- Publication date Jan 5, 2006
- Matrix Semiconductor, Inc.
- Usha Raghuram
- H01 - BASIC ELECTRIC ELEMENTS

Usha Raghuram

Person

Patents Grantslast 30 patents

Pillar devices and methods of making thereof

Patterning of submicron pillars in a memory array

Methods for protecting patterned features during trench etch

Dual damascene with amorphous carbon for 3D deep via/trench applica...

Diode array and method of making thereof

Method of making a nonvolatile phase change memory cell having a re...

Modified DARC stack for resist patterning

Liner for tungsten/silicon dioxide interface in memory

Method for reducing dielectric overetch using a dielectric etch sto...

Method of plasma etching transition metal oxides

Method for forming doped polysilicon via connecting polysilicon layers

Method for forming doped polysilicon via connecting polysilicon layers

Pillar devices and methods of making thereof

Diode array and method of making thereof

Method for reducing dielectric overetch using a dielectric etch sto...

Nonvolatile phase change memory cell having a reduced contact area

Conductive hard mask to protect patterned features during trench etch

Doped polysilicon via connecting polysilicon layers

Method for patterning submicron pillars

Method for reducing dielectric overetch using a dielectric etch sto...

Nonselective unpatterned etchback to expose buried patterned features

Method for etching and/or patterning a silicon-containing layer

Method of forming contact openings

Plasma etching method

Plasma etching method

Patents Applicationslast 30 patents

METHODS FOR PROTECTING PATTERNED FEATURES DURING TRENCH ETCH

METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STO...

PILLAR DEVICES AND METHODS OF MAKING THEREOF

Diode Array and Method of Making Thereof

METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS

METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STO...

CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH

METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS

Modified darc stack for resist patterning

PATTERNING OF SUBMICRON PILLARS IN A MEMORY ARRAY

Pillar devices and methods of making thereof

DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICA...

DIODE ARRAY AND METHOD OF MAKING THEREOF

LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY

Method for reducing dielectric overetch using a dielectric etch sto...

NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED CONTACT AREA

METHOD OF MAKING A NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A RE...

Conductive hard mask to protect patterned features during trench etch

Method of plasma etching transition metals and their compounds

Method for reducing dielectric overetch using a dielectric etch sto...

Method for patterning submicron pillars

Doped polysilicon via connecting polysilicon layers

Nonselective unpatterned etchback to expose buried patterned features