Uway Tseng

Person

Houli Shiang, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Big via structure
- Patent number 8,716,871
- Issue date May 6, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS image sensor big via bonding pad application for AICu process
- Patent number 8,680,635
- Issue date Mar 25, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power devices having reduced on-resistance and methods of their man...
- Patent number 8,633,086
- Issue date Jan 21, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Alex Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS image sensor big via bonding pad application for AlCu Process
- Patent number 8,502,335
- Issue date Aug 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS image sensor big via bonding pad application for AICu process
- Patent number 8,344,471
- Issue date Jan 1, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene with via liner
- Patent number 7,884,013
- Issue date Feb 8, 2011
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory device having a nitride barrier to reduce the f...
- Patent number 7,400,011
- Issue date Jul 15, 2008
- Macronix International Co. Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene with via liner
- Patent number 7,387,961
- Issue date Jun 17, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory device having a nitride barrier to reduce the f...
- Patent number 7,199,007
- Issue date Apr 3, 2007
- Macronix International Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a memory device having a self-aligned contact
- Patent number 6,960,506
- Issue date Nov 1, 2005
- Macronix International Co., Ltd.
- Hung-Yu Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing charge loss for nonvolatile memory
- Patent number 6,746,968
- Issue date Jun 8, 2004
- Macronix International Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating cobalt salicide contact
- Patent number 6,734,098
- Issue date May 11, 2004
- Macronix International Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a non-volatile memory device to eliminate cha...
- Patent number 6,713,388
- Issue date Mar 30, 2004
- Macronix International Co. Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming gate
- Patent number 6,562,682
- Issue date May 13, 2003
- Macronix International Co., Ltd.
- Hung-Yu Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating an ONO layer of an NROM
- Patent number 6,548,425
- Issue date Apr 15, 2003
- Macronix International Co. Ltd.
- Kent Kuohua Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a low loss dielectric layer in the tungsten chem...
- Patent number 6,511,907
- Issue date Jan 28, 2003
- Macronix International Co., Ltd.
- Jung-Yu Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of gettering layer for improving chemical-mechanical polishi...
- Patent number 6,413,840
- Issue date Jul 2, 2002
- Macronix International Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NOVEL PROCESS FOR FORMING A BIG VIA
- Publication number 20130207276
- Publication date Aug 15, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Image Sensor Big Via Bonding Pad Application for AICu Process
- Publication number 20130134543
- Publication date May 30, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MAN...
- Publication number 20110156217
- Publication date Jun 30, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Alex Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AICu PROCESS
- Publication number 20110024866
- Publication date Feb 3, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AlCu PROCESS
- Publication number 20110024867
- Publication date Feb 3, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene with via liner
- Publication number 20080230919
- Publication date Sep 25, 2008
- Taiwan Semiconductor Manufacturing Co., LTD
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME
- Publication number 20070178664
- Publication date Aug 2, 2007
- Taiwan Semiconductor Manufacturing Co., LTD
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory device having a nitride barrier to reduce the f...
- Publication number 20070155100
- Publication date Jul 5, 2007
- MACRONIX INTERNATIONAL CO., LTD
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate electrode and MOS transistor including gate and method of fabr...
- Publication number 20070102748
- Publication date May 10, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow trench isolation structure and method of fabricating the same
- Publication number 20070020877
- Publication date Jan 25, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene with via liner
- Publication number 20060170106
- Publication date Aug 3, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a memory device having a self-aligned contact
- Publication number 20050106819
- Publication date May 19, 2005
- Hung-Yu Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory device having a nitride barrier to reduce the f...
- Publication number 20040229437
- Publication date Nov 18, 2004
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating cobalt salicide contact
- Publication number 20040029376
- Publication date Feb 12, 2004
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a non-volatile memory device to eliminate cha...
- Publication number 20030003658
- Publication date Jan 2, 2003
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating an ONO layer of an NROM
- Publication number 20020168875
- Publication date Nov 14, 2002
- Kent Kuohua Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a via of a dual damascene with low resistance
- Publication number 20020123219
- Publication date Sep 5, 2002
- Jerald Laverty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming contacts of memory devices using an etch stop layer
- Publication number 20020119618
- Publication date Aug 29, 2002
- MACRONIX INTERNATIONAL CO., LTD
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improving contact reliability in semiconductor devices
- Publication number 20020072217
- Publication date Jun 13, 2002
- MACRONIX INTERNATIONAL CO., LTD
- Uway Tseng
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Big via structure

CMOS image sensor big via bonding pad application for AICu process

Power devices having reduced on-resistance and methods of their man...

CMOS image sensor big via bonding pad application for AlCu Process

CMOS image sensor big via bonding pad application for AICu process

Dual damascene with via liner

Non-volatile memory device having a nitride barrier to reduce the f...

Dual damascene with via liner

Non-volatile memory device having a nitride barrier to reduce the f...

Method of fabricating a memory device having a self-aligned contact

Method of reducing charge loss for nonvolatile memory

Method for fabricating cobalt salicide contact

Method of fabricating a non-volatile memory device to eliminate cha...

Method for forming gate

Method for fabricating an ONO layer of an NROM

Method for forming a low loss dielectric layer in the tungsten chem...

Method of gettering layer for improving chemical-mechanical polishi...

Patents Applicationslast 30 patents

NOVEL PROCESS FOR FORMING A BIG VIA

CMOS Image Sensor Big Via Bonding Pad Application for AICu Process

POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MAN...

CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AICu PROCESS

CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AlCu PROCESS

Dual damascene with via liner

SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME

Non-volatile memory device having a nitride barrier to reduce the f...

Gate electrode and MOS transistor including gate and method of fabr...

Shallow trench isolation structure and method of fabricating the same

Dual damascene with via liner

Method of fabricating a memory device having a self-aligned contact

Non-volatile memory device having a nitride barrier to reduce the f...

Method for fabricating cobalt salicide contact

Method of fabricating a non-volatile memory device to eliminate cha...

Method for fabricating an ONO layer of an NROM

Method of forming a via of a dual damascene with low resistance

Method for forming contacts of memory devices using an etch stop layer

Method for improving contact reliability in semiconductor devices