Valerie H. CHICKANOSKY

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory built-in self test error correcting code (MBIST ECC) for low...
- Patent number 10,950,325
- Issue date Mar 16, 2021
- Marvell Asia Pte., Ltd.
- Deepak I. Hanagandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failure analysis and repair register sharing for memory BIST
- Patent number 10,014,074
- Issue date Jul 3, 2018
- GLOBALFOUNDRIES Inc.
- Krishnendu Mondal
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for efficient memory repair
- Patent number 8,612,813
- Issue date Dec 17, 2013
- International Business Machines Corporation
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for efficient memory repair
- Patent number 8,381,052
- Issue date Feb 19, 2013
- International Business Machines Corporation
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatically extensible addressing for shared array built-in self-...
- Patent number 7,757,141
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Valerie H. Chickanosky
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for self identification of circuitry
- Patent number 7,735,031
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Valerie Hornbeck Chickanosky
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for fine position adjustment using phase in a...
- Patent number 6,937,414
- Issue date Aug 30, 2005
- Hitachi Global Storage Technologies Netherlands B.V.
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Grant
Read channel with automatic servo track writer
- Patent number 6,934,103
- Issue date Aug 23, 2005
- Hitachi Global Storage Technologies Netherlands B.V.
- Valerie Chickanosky
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY BUILT-IN SELF TEST ERROR CORRECTING CODE (MBIST ECC) FOR LOW...
- Publication number 20200321070
- Publication date Oct 8, 2020
- Marvell International Ltd.
- Deepak I. HANAGANDI
- G11 - INFORMATION STORAGE
Information Patent Application
FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST
- Publication number 20170309349
- Publication date Oct 26, 2017
- GLOBALFOUNDRIES INC.
- Krishnendu MONDAL
- G11 - INFORMATION STORAGE
Information Patent Application
STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
- Publication number 20140129888
- Publication date May 8, 2014
- International Business Machines Corporation
- Valerie H. Chickanosky
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
- Publication number 20130139010
- Publication date May 30, 2013
- International Business Machines Corporation
- Valerie H. CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
- Publication number 20110113280
- Publication date May 12, 2011
- International Business Machines Corporation
- Valerie H. CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST
- Publication number 20110029827
- Publication date Feb 3, 2011
- International Business Machines Corporation
- VALERIE H CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-...
- Publication number 20090249146
- Publication date Oct 1, 2009
- International Business Machines Corporation
- Valerie H. CHICKANOSKY
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY
- Publication number 20090052609
- Publication date Feb 26, 2009
- Valerie Hornbeck Chickanosky
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INT...
- Publication number 20080046789
- Publication date Feb 21, 2008
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for fine position adjustment using phase in a...
- Publication number 20040090694
- Publication date May 13, 2004
- International Business Machines Corporation
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Application
Read channel with automatic servo track writer
- Publication number 20040090695
- Publication date May 13, 2004
- International Business Machines Corporation
- Valerie Chickanosky
- G11 - INFORMATION STORAGE

Valerie H. CHICKANOSKY

Person

Patents Grantslast 30 patents

Memory built-in self test error correcting code (MBIST ECC) for low...

Failure analysis and repair register sharing for memory BIST

Circuit and method for efficient memory repair

Circuit and method for efficient memory repair

Automatically extensible addressing for shared array built-in self-...

Method and apparatus for self identification of circuitry

Method and apparatus for fine position adjustment using phase in a...

Read channel with automatic servo track writer

Patents Applicationslast 30 patents

MEMORY BUILT-IN SELF TEST ERROR CORRECTING CODE (MBIST ECC) FOR LOW...

FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST

STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES

CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR

CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR

METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST

AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-...

METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY

APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INT...

Method and apparatus for fine position adjustment using phase in a...

Read channel with automatic servo track writer