APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS

Abstract

This patent describes a method for varying the amplitude and frequency of power supply oscillations produced by content addressable memories or other critical circuits using BIST. Supply oscillations are produced by performing noisy (high switching activity—high current demand) searches followed by quiet (low switching activity—low current demand) searches. The amplitude and frequency of oscillations can be varied by changing the number of noisy and quiet searches e.g. pattern 1-noisy quiet, noisy, quiet; pattern 2-noisy, noisy, quiet, noisy, noisy, quiet, etc. By going through different patterns the current demand from the CAM macro increases the likelihood of producing worst—case noise and enables testing of CAM operation as well as surrounding circuitry in these noisy conditions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates an example of General CAM Architecture

FIG. 2 illustrates CAM induced power supply compression

FIG. 3 illustrates a sample current demand from a single noisy CAM search:

FIG. 4 illustrates a sample current demand from four noisy CAM searches and

FIG. 5 illustrates power supply voltage compression caused by 1, 2 or 4 noisy searches each followed by quiet cycles.

The following detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to the drawings in greater detail, we will discuss the architecture and operation of the CAM and technique to generate noise using built in system test (BIST) circuits to test memory and adjacent circuits.

Content Addressable Memory (CAM) is an application specific memory designed to accelerate the search of large look-up tables. CAM is commonly used for applications such as address translation in network routers, TLBs in processor caches, pattern recognition, and data compression. CAM is an attractive solution for these applications because it performs a fully parallel search of the entire look-up table, and, regardless of table size, returns a search result within nanoseconds. FIG. 1 shows a simple CAM architecture that illustrates how this fast search operation is performed. During the search operation the search data in the Search Word Register is supplied to every CAM word via Search-Lines (SLs), compared to every stored word in every entry, and the results of this comparison are displayed on all Match-Lines (MLs). Since both SLs and MLs are highly capacitive and switch every search cycle, CAM causes high power consumption and severe on-chip supply noise.

During a search operation, CAM can draw high current (I_DD), causing significant power supply voltage compression in the form of VDD droop and GND bounce. FIG. 2 shows a typical CAM voltage compression waveform for a CAM using virtual-GND pre-charge-high ML sensing scheme. This waveform illustrates the SL and ML components, which cause the high voltage compression. Without the heavy use of decoupling capacitance, which is both area and yield expensive, this CAM sensing can cause voltage compression exceeding ½ V_DD. This power-supply noise is especially of concern in Embedded CAM (eCAM), which shares its environment with noise-sensitive circuits. The large supply voltage compression can not only cause failure in the CAM but also affect the neighboring circuits that may be noise-sensitive. Technology scaling further aggravates this problem by decreasing voltage headroom while increasing both current density, which exacerbates the resistive voltage drop, and transition speed, which enlarges Ldi/dt noise.

FIG. 3 illustrates a current profile for a CAM performing a single noisy search. Peaks in the current occur during search-line switching, match-line switching, and field output switching. FIG. 4 illustrates the current demand of a power supply during four noisy searches. FIG. 5 illustrates the effect of one, two, and four noisy searches on the power supply. The BIST is programmed in accordance with the present invention to provide the worst-case scenario described previously, the peaks and troughs created by the noise demand will match up with the critical frequency of the particular chip environment of each ASIC CAM design, so that it will cause the most damage in terms of the noise-induced fails. It is necessary therefore to be able to determine the frequency and amplitude of the power delivery system oscillations that produce the worst-case noise.

Since the amplitude and frequency will vary for each ASIC design using CAM, it is necessary to provide a means to obtain the Q point for the worst-case condition of each individual ASIC design to excite or disturb the power supply system thereby injecting the noise into the ASIC under test. The ASIC design must initially be exercised by the BIST under controlled conditions to determine the worst-case condition.

The BIST patterns are used to change the switching of the CAM to vary the amplitude and frequency of the power delivery system in order to produce the worst-case noise condition and the Q point of the ASIC design under study. These patterns should test the effects of the power-supply compression and preferably use noisy cycles followed by quiet cycles using a programmable BIST in order to produce high switching activity-high current demand and low switching activity-low current demand. Such patterns include generating:

• 1. noisy matches followed by quiet matches; or
• 2. noisy search followed by quiet mismatches; or
• 3. matches followed by all-bit mismatches; or
• 4. single bit mismatch (noisy followed by quiet cycles),Each of these patterns has the potential to produce the worst-case condition depending on the ASIC design under test. It should be understood that the details of these patterns are given by way of examples and that other patterns may also be used in keeping within the scope of the present invention.

For example, the first pattern performs a noisy-quiet-noisy-quiet match sequence. Where the number of consecutive noisy searches can be varied from 1 to 16 and the number of consecutive quiet searches can be independently varied from 1 to 16. This pattern generates a current demand that has a variable frequency and allows the BIST to zero in on the critical frequency of the power supply net. When the worst case power supply noise is induced the CAM as well as other adjacent circuits sensitive to noise can be tested for proper functionality.

The second pattern performs a noisy match-noisy mismatch-quiet mismatch-noisy match-noisy mismatch-quiet mismatch sequence. The number of consecutive noisy match, noisy mismatch pairs can be varied from 1 to 16. The number of consecutive quiet mismatch cycles can be independently varied from 1 to 16. This pattern activates a number of high current demand circuits in the CAM while also testing power supply noise sensitive operations. Like the previous pattern this pattern can also be used to generate noise to test other CAM adjacent circuits that may be sensitive to noise.

The third pattern performs a noisy match-noisy mismatch sequence. The number of consecutive matches can be varied from 1 to 16. The number of mismatches can be independently varied from 1 to 16. This pattern generates noise due to switching of lines, match-lines, field outputs, and macro outputs. The pattern tests the effects of noise on the ability of match-line to pull up to the match voltage as well as discharge to the mismatch voltage. It can also be used to generate noise to test other adjacent circuits that may be sensitive to noise.

The fourth pattern performs a noisy single bit mismatch-quiet single bit mismatch sequence. The number of noisy single-bit mismatch cycles can be varied from 1 to 16. The number of quiet single-bit mismatch cycles can be independently varied from 1 to 16. This pattern generates noise by activating another subset of high current demand circuits and then testing another set of sensitive operations. It can also be used to generate noise to test other adjacent circuits that may be sensitive to noise.

While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims

1. Method for testing an integrated circuit having a critical noise generating circuit comprising: providing an integrated circuit having a power delivery system and the critical circuit;switching the critical circuit with a predetermined pattern to generate significant current fluctuations to produce a critical amount of power supply noise.

2. The method of claim 1 wherein the critical circuit is a memory device.

3. The method of claim 2 wherein the memory device is a CAM.

4. The method of claim 3 wherein the switching occurs during search operation.

5. The method of claim 1 wherein the switching is generated by a programmable BIST using a test pattern.

6. The method of claim 5 wherein the test pattern produces a worst-case noise condition for the integrated circuit.

7. The method claim 6 wherein the test pattern performs a series of noisy—quiet match sequences.

8. The method of claim 6 wherein the test pattern performs a series of noisy searches followed by quiet mismatches.

9. The method of claim 6 wherein the test pattern performs a noisy match followed by noisy mismatches.

10. The method of claim 6 wherein the test pattern performs a single bit noisy mismatch followed by single bit quiet mismatch cycles.

11. Apparatus for testing an integrated circuit having multiple circuits and a critical noise generating circuit comprising: a power distribution system with an output that supplies power to the circuits and the critical noise generating circuit;the critical noise generating circuit that causes significant current fluctuations when switched;a device that switches the critical noise generating circuit with a predetermined pattern to produce a critical amount of power supply noise.

12. The apparatus of claim 11 wherein the device used for switching is a programmable BIST, which generates test patterns to the memory device to produce a worst-case noise condition for the integrated circuit.

13. The apparatus of claim 11 wherein the critical noise generating circuit is a memory device.

14. The apparatus of claim 13 wherein the memory device is a CAM.

15. The apparatus of claiml4 wherein the CAM is switched during search operation.

16. The apparatus of claim 15 the CAM has match lines and search lines, which cause current fluctuations when switched;

17. The apparatus of claim 13 wherein the test pattern performs a series of noisy—quiet match sequences.

18. The apparatus of claim 13 wherein the test pattern performs a series of noisy searches followed by quiet mismatches.

19. The apparatus of claim 13 wherein the test pattern performs a noisy match followed by noisy mismatches.

20. The apparatus of claim 13 wherein the test pattern performs a single bit noisy mismatch followed by single bit quiet mismatch cycles.