Vernon P Norman

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and arrangements for link power reduction
- Patent number 8,130,887
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
One-sample-per-bit decision feedback equalizer (DFE) clock and data...
- Patent number 7,809,054
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Juan A. Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for manufacturing a calibration device
- Patent number 7,698,802
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Grant
Using statistical signatures for testing high-speed circuits
- Patent number 7,661,052
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- G01 - MEASURING TESTING
Information Patent Grant
Unified digital architecture
- Patent number 7,646,839
- Issue date Jan 12, 2010
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Impedance calibration for source series terminated serial link tran...
- Patent number 7,570,071
- Issue date Aug 4, 2009
- International Business Machines Corporation
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Grant
Altering power consumption in communication links based on measured...
- Patent number 7,567,614
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Juan Antonio Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Overshoot reduction in VCO calibration for serial link phase lock l...
- Patent number 7,539,473
- Issue date May 26, 2009
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating random jitter
- Patent number 7,512,177
- Issue date Mar 31, 2009
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
method for providing automatic adaptation to frequency offsets in h...
- Patent number 7,477,713
- Issue date Jan 13, 2009
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock data recovering system with external early/late input
- Patent number 7,418,069
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Martin Schmatz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Altering power consumption in communication links based on measured...
- Patent number 7,418,032
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Juan Antonio Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and arrangements for link power reduction
- Patent number 7,397,876
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Impedance calibration for source series terminated serial link tran...
- Patent number 7,368,902
- Issue date May 6, 2008
- International Business Machines Corporation
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for data and edge detection with correlation tables
- Patent number 7,349,498
- Issue date Mar 25, 2008
- International Business Machines Corporation
- Hayden C Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for using statistical signatures for testing high...
- Patent number 7,340,660
- Issue date Mar 4, 2008
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- G01 - MEASURING TESTING
Information Patent Grant
Digital adaptive control loop for data deserialization
- Patent number 7,317,777
- Issue date Jan 8, 2008
- International Business Machines Corporation
- Hayden C Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock data recovering system with external early/late input
- Patent number 7,315,594
- Issue date Jan 1, 2008
- International Business Machines Corporation
- Martin Schmatz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for determining jitter of a signal in a serial link and high...
- Patent number 7,295,604
- Issue date Nov 13, 2007
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for high frequency clock signal gating
- Patent number 7,279,950
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Receiver for clock and data recovery and method for calibrating sam...
- Patent number 7,149,269
- Issue date Dec 12, 2006
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Analog unidirectional serial link architecture
- Patent number 7,142,624
- Issue date Nov 28, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for providing quality control on wafers running o...
- Patent number 7,089,132
- Issue date Aug 8, 2006
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Fast detection of incorrect sampling in an oversampling clock and d...
- Patent number 7,085,970
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Gareth J. Nicholls
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture for advanced serial link between two cards
- Patent number 7,082,484
- Issue date Jul 25, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for reducing jitter in a PLL of high speed seria...
- Patent number 7,042,277
- Issue date May 9, 2006
- International Business Machines Corporation
- Hayden C. Cranford, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for oversampling with evenly spaced samples
- Patent number 6,999,544
- Issue date Feb 14, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Analog unidirectional serial link architecture
- Patent number 6,993,107
- Issue date Jan 31, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Self-adaptive voltage regulator for a phase-locked loop
- Patent number 6,977,558
- Issue date Dec 20, 2005
- International Busines Machines Corporation
- Hayden C. Cranford, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Unified digital architecture
- Patent number 6,970,529
- Issue date Nov 29, 2005
- International Business Machines Corporation
- Hayden Clavie Cranford, Jr.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN...
- Publication number 20090116593
- Publication date May 7, 2009
- International Business Machines Corporation
- HAYDEN C. CRANFORD, JR.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and Arrangements for Link Power Reduction
- Publication number 20080285695
- Publication date Nov 20, 2008
- Hayden Clavie Cranford, JR.
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE)...
- Publication number 20080240224
- Publication date Oct 2, 2008
- JUAN A. CARBALLO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ALTERING POWER CONSUMPTION IN COMMUNICATION LINKS BASED ON MEASURED...
- Publication number 20080232530
- Publication date Sep 25, 2008
- International Business Machines Corporation
- Juan Antonio Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR GENERATING RANDOM JITTER
- Publication number 20080150599
- Publication date Jun 26, 2008
- International Business Machines Corporation
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USING STATISTICAL SIGNATURES FOR TESTING HIGH-SPEED CIRCUITS
- Publication number 20080133164
- Publication date Jun 5, 2008
- International Business Machines Corporation
- Hayden C. Cranford
- G01 - MEASURING TESTING
Information Patent Application
Impedance Calibration for Source Series Terminated Serial Link Tran...
- Publication number 20080122452
- Publication date May 29, 2008
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Application
Impedance Calibration for Source Series Terminated Serial Link Tran...
- Publication number 20080120838
- Publication date May 29, 2008
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Application
Clock Data Recovering System with External Early/Late Input
- Publication number 20080112521
- Publication date May 15, 2008
- Martin Schmatz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING
- Publication number 20070279117
- Publication date Dec 6, 2007
- International Business Machines Corporation
- Hayden C. Cranford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Overshoot reduction in VCO calibration for serial link phase lock l...
- Publication number 20070254613
- Publication date Nov 1, 2007
- Hayden C. Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
One-sample-per-bit decision feedback equalizer (DFE) clock and data...
- Publication number 20070242741
- Publication date Oct 18, 2007
- Juan A. Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Impedance calibration for source series terminated serial link tran...
- Publication number 20070096720
- Publication date May 3, 2007
- Steven M. Clements
- G01 - MEASURING TESTING
Information Patent Application
Method and system for high frequency clock signal gating
- Publication number 20070069793
- Publication date Mar 29, 2007
- International Business Machines Corporation
- Hayden C. Cranford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-rate SERDES receiver
- Publication number 20070047589
- Publication date Mar 1, 2007
- Bobak Modaress-Razavi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Altering power consumption in communication links based on measured...
- Publication number 20060209944
- Publication date Sep 21, 2006
- Juan Antonio Carballo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and arrangements for link power reduction
- Publication number 20060045224
- Publication date Mar 2, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Unified digital architecture
- Publication number 20060029177
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Analog unidirectional serial link architecture
- Publication number 20060008042
- Publication date Jan 12, 2006
- International Business Machines Corporation
- Hayden Clavie Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR PROVIDING QUALITY CONTROL ON WAFERS RUNNING O...
- Publication number 20050267705
- Publication date Dec 1, 2005
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
Circuit and method for providing automatic adaptation to frequency...
- Publication number 20050195863
- Publication date Sep 8, 2005
- International Business Machines Corporation
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for determining jitter of a signal in a serial link and high...
- Publication number 20050111536
- Publication date May 26, 2005
- International Business Machines Corporation
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Circuit and method for reducing jitter in a PLL of high speed seria...
- Publication number 20050077936
- Publication date Apr 14, 2005
- International Business Machines Corporation
- Hayden C. Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and system for using statistical signatures for testing high...
- Publication number 20050076279
- Publication date Apr 7, 2005
- International Business Machines Corporation
- Hayden C. Cranford
- G01 - MEASURING TESTING
Information Patent Application
Self-adaptive voltage regulator for a phase-locked loop
- Publication number 20050046489
- Publication date Mar 3, 2005
- International Business Machines Corporation
- Hayden C. Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock data recovering system with external early/late input
- Publication number 20040208270
- Publication date Oct 21, 2004
- Martin Schmatz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Receiver for clock and data recovery and method for calibrating sam...
- Publication number 20040170244
- Publication date Sep 2, 2004
- International Business Machines Corporation
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for data and edge detection with correlation tables
- Publication number 20040066864
- Publication date Apr 8, 2004
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital adaptive control loop for data deserialization
- Publication number 20040066871
- Publication date Apr 8, 2004
- Hayden C. Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Fast detection of incorrect sampling in an oversampling clock and d...
- Publication number 20040019837
- Publication date Jan 29, 2004
- International Business Machines Corporation
- Gareth J. Nicholls
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Vernon P Norman

Person

Patents Grantslast 30 patents

Method and arrangements for link power reduction

One-sample-per-bit decision feedback equalizer (DFE) clock and data...

Method for manufacturing a calibration device

Using statistical signatures for testing high-speed circuits

Unified digital architecture

Impedance calibration for source series terminated serial link tran...

Altering power consumption in communication links based on measured...

Overshoot reduction in VCO calibration for serial link phase lock l...

Method and apparatus for generating random jitter

method for providing automatic adaptation to frequency offsets in h...

Clock data recovering system with external early/late input

Altering power consumption in communication links based on measured...

Methods and arrangements for link power reduction

Impedance calibration for source series terminated serial link tran...

Method and system for data and edge detection with correlation tables

Method and system for using statistical signatures for testing high...

Digital adaptive control loop for data deserialization

Clock data recovering system with external early/late input

Method for determining jitter of a signal in a serial link and high...

Method and system for high frequency clock signal gating

Receiver for clock and data recovery and method for calibrating sam...

Analog unidirectional serial link architecture

Method and system for providing quality control on wafers running o...

Fast detection of incorrect sampling in an oversampling clock and d...

Architecture for advanced serial link between two cards

Circuit and method for reducing jitter in a PLL of high speed seria...

Apparatus and method for oversampling with evenly spaced samples

Analog unidirectional serial link architecture

Self-adaptive voltage regulator for a phase-locked loop

Unified digital architecture

Patents Applicationslast 30 patents

CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN...

Method and Arrangements for Link Power Reduction

STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE)...

ALTERING POWER CONSUMPTION IN COMMUNICATION LINKS BASED ON MEASURED...

METHOD AND APPARATUS FOR GENERATING RANDOM JITTER

USING STATISTICAL SIGNATURES FOR TESTING HIGH-SPEED CIRCUITS

Impedance Calibration for Source Series Terminated Serial Link Tran...

Impedance Calibration for Source Series Terminated Serial Link Tran...

Clock Data Recovering System with External Early/Late Input

METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING

Overshoot reduction in VCO calibration for serial link phase lock l...

One-sample-per-bit decision feedback equalizer (DFE) clock and data...

Impedance calibration for source series terminated serial link tran...

Method and system for high frequency clock signal gating

Multi-rate SERDES receiver

Altering power consumption in communication links based on measured...

Methods and arrangements for link power reduction

Unified digital architecture

Analog unidirectional serial link architecture

METHOD AND SYSTEM FOR PROVIDING QUALITY CONTROL ON WAFERS RUNNING O...

Circuit and method for providing automatic adaptation to frequency...

Method for determining jitter of a signal in a serial link and high...

Circuit and method for reducing jitter in a PLL of high speed seria...

Method and system for using statistical signatures for testing high...

Self-adaptive voltage regulator for a phase-locked loop

Clock data recovering system with external early/late input

Receiver for clock and data recovery and method for calibrating sam...

Method and system for data and edge detection with correlation tables

Digital adaptive control loop for data deserialization

Fast detection of incorrect sampling in an oversampling clock and d...