Vidyadhara Bellippady

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 8,258,567
- Issue date Sep 4, 2012
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array and control method for flash based FPGA cell
- Patent number 8,120,955
- Issue date Feb 21, 2012
- Actel Corporation
- Zhigang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,956,404
- Issue date Jun 7, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,915,665
- Issue date Mar 29, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,898,018
- Issue date Mar 1, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PLD providing soft wakeup logic
- Patent number 7,884,640
- Issue date Feb 8, 2011
- Actel Corporation
- Jonathan W Greene
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radiation-tolerant flash-based FPGA memory cells
- Patent number 7,768,317
- Issue date Aug 3, 2010
- Actel Corporation
- Fethi Dhaoui
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,573,093
- Issue date Aug 11, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,538,379
- Issue date May 26, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,538,382
- Issue date May 26, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with source-side column select
- Patent number 7,522,453
- Issue date Apr 21, 2009
- Actel Corporation
- Zhigang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,501,681
- Issue date Mar 10, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,473,960
- Issue date Jan 6, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,285,818
- Issue date Oct 23, 2007
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20110147821
- Publication date Jun 23, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAY AND CONTROL METHOD FOR FLASH BASED FPGA CELL
- Publication number 20100208520
- Publication date Aug 19, 2010
- Actel Corporation
- Zhigang Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD PROVIDING SOFT WAKEUP LOGIC
- Publication number 20100156457
- Publication date Jun 24, 2010
- Actel Corporation
- Jonathan W. Greene
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20100038697
- Publication date Feb 18, 2010
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20090212343
- Publication date Aug 27, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20090159954
- Publication date Jun 25, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20080093654
- Publication date Apr 24, 2008
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20070215935
- Publication date Sep 20, 2007
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile two-transistor programmable logic cell and array layout
- Publication number 20060284238
- Publication date Dec 21, 2006
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS

Vidyadhara Bellippady

Person

Patents Grantslast 30 patents

Non-volatile two-transistor programmable logic cell and array layout

Array and control method for flash based FPGA cell

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

PLD providing soft wakeup logic

Radiation-tolerant flash-based FPGA memory cells

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile memory with source-side column select

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Patents Applicationslast 30 patents

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

ARRAY AND CONTROL METHOD FOR FLASH BASED FPGA CELL

PLD PROVIDING SOFT WAKEUP LOGIC

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

Non-volatile two-transistor programmable logic cell and array layout