Vijai Kumar N. Chhagan

Person

Leicester, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating local metal interconnections with low contac...
- Patent number 6,534,393
- Issue date Mar 18, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Mei Sheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form self-aligned, L-shaped sidewall spacers
- Patent number 6,391,732
- Issue date May 21, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an extended metal gate using a damascene process
- Patent number 6,387,765
- Issue date May 14, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Vijai Kumar Chhagan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an L-shaped spacer using a disposable polysilico...
- Patent number 6,346,468
- Issue date Feb 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Ramachandramurthy Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an extended metal gate using a damascene process
- Patent number 6,303,447
- Issue date Oct 16, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Vijai Komar Chhagan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate a floating gate with a sloping sidewall for a f...
- Patent number 6,284,637
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Vijai Komar N. Chhagan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LOCOS mask for suppression of narrow space field oxide thinning and...
- Patent number 6,249,035
- Issue date Jun 19, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Igor V. Peidous
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form self-sealing air gaps between metal interconnects
- Patent number 6,228,770
- Issue date May 8, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Yelehanka Ramachandramurthy Pradeep
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Locos mask for suppression of narrow space field oxide thinning and...
- Patent number 6,071,793
- Issue date Jun 6, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Igor V. Peidous
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method to form self-aligned, L-shaped sidewall spacers
- Publication number 20020076877
- Publication date Jun 20, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming an extended metal gate using a damascene process
- Publication number 20020006715
- Publication date Jan 17, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Vijai Komar Chhagan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate a floating gate with a sloping sidewall for a f...
- Publication number 20020000604
- Publication date Jan 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Vijai Komar N. Chhagan
- H01 - BASIC ELECTRIC ELEMENTS

Vijai Kumar N. Chhagan

Person

Patents Grantslast 30 patents

Method for fabricating local metal interconnections with low contac...

Method to form self-aligned, L-shaped sidewall spacers

Method for forming an extended metal gate using a damascene process

Method for forming an L-shaped spacer using a disposable polysilico...

Method for forming an extended metal gate using a damascene process

Method to fabricate a floating gate with a sloping sidewall for a f...

LOCOS mask for suppression of narrow space field oxide thinning and...

Method to form self-sealing air gaps between metal interconnects

Locos mask for suppression of narrow space field oxide thinning and...

Patents Applicationslast 30 patents

Method to form self-aligned, L-shaped sidewall spacers

Method for forming an extended metal gate using a damascene process

Method to fabricate a floating gate with a sloping sidewall for a f...