Vikas Agarwal

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked multiple-input delay gates
- Patent number 9,122,823
- Issue date Sep 1, 2015
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for stacked CMOS circuits
- Patent number 8,904,322
- Issue date Dec 2, 2014
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Statistical method for hierarchically routing layout utilizing flat...
- Patent number 8,356,267
- Issue date Jan 15, 2013
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolating faulty decoupling capacitors
- Patent number 8,009,398
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for self-contained automatic decoupling capaci...
- Patent number 7,750,511
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for dependency tracking and flush recovery for an...
- Patent number 7,660,971
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data shifting through scan registers
- Patent number 7,551,475
- Issue date Jun 23, 2009
- International Business Machines Corporation
- Vikas Agarwal
- G01 - MEASURING TESTING
Information Patent Grant
System and computer program for verifying performance of an array b...
- Patent number 7,552,413
- Issue date Jun 23, 2009
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-saving circuit and method using charge equalization across c...
- Patent number 7,545,176
- Issue date Jun 9, 2009
- International Business Machines Corporation
- Vikas Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient dynamic register file design for multiple simultaneous bi...
- Patent number 7,536,395
- Issue date May 19, 2009
- International Business Machines Corporation
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Shift register latch with embedded dynamic random access memory sca...
- Patent number 7,474,574
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for verifying performance of an array by simulating operatio...
- Patent number 7,424,691
- Issue date Sep 9, 2008
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STACKED MULTIPLE-INPUT DELAY GATES
- Publication number 20150178427
- Publication date Jun 25, 2015
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR STACKED CMOS CIRCUITS
- Publication number 20140298282
- Publication date Oct 2, 2014
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT...
- Publication number 20120110536
- Publication date May 3, 2012
- International Business Machines Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOLATING FAULTY DECOUPLING CAPACITORS
- Publication number 20100308663
- Publication date Dec 9, 2010
- International Business Machines Corporation
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS C...
- Publication number 20090108920
- Publication date Apr 30, 2009
- Vikas Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCA...
- Publication number 20090010077
- Publication date Jan 8, 2009
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY B...
- Publication number 20080270963
- Publication date Oct 30, 2008
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Self-Contained Automatic Decoupling Capaci...
- Publication number 20080251888
- Publication date Oct 16, 2008
- IBM Corporation
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Dependency Tracking and Flush Recovery for an...
- Publication number 20080189535
- Publication date Aug 7, 2008
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Floating Bitlines in Static Random Access Memory Arrays
- Publication number 20080123437
- Publication date May 29, 2008
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT DYNAMIC REGISTER FILE DESIGN FOR MULTIPLE SIMULTANEOUS BI...
- Publication number 20070282865
- Publication date Dec 6, 2007
- Vikas Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
Method and System for Verifying Performance of an Array by Simulati...
- Publication number 20070245279
- Publication date Oct 18, 2007
- Vikas Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA SHIFT CAPABILITY FOR SCANNABLE REGISTER
- Publication number 20070240023
- Publication date Oct 11, 2007
- Vikas Agarwal
- G01 - MEASURING TESTING

Vikas Agarwal

Person

Patents Grantslast 30 patents

Stacked multiple-input delay gates

Structure for stacked CMOS circuits

Statistical method for hierarchically routing layout utilizing flat...

Isolating faulty decoupling capacitors

Method and apparatus for self-contained automatic decoupling capaci...

Method and system for dependency tracking and flush recovery for an...

Data shifting through scan registers

System and computer program for verifying performance of an array b...

Energy-saving circuit and method using charge equalization across c...

Efficient dynamic register file design for multiple simultaneous bi...

Shift register latch with embedded dynamic random access memory sca...

Method for verifying performance of an array by simulating operatio...

Patents Applicationslast 30 patents

STACKED MULTIPLE-INPUT DELAY GATES

DESIGN STRUCTURE FOR STACKED CMOS CIRCUITS

STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT...

ISOLATING FAULTY DECOUPLING CAPACITORS

ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS C...

SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCA...

SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY B...

Method and Apparatus for Self-Contained Automatic Decoupling Capaci...

Method and System for Dependency Tracking and Flush Recovery for an...

Apparatus for Floating Bitlines in Static Random Access Memory Arrays

EFFICIENT DYNAMIC REGISTER FILE DESIGN FOR MULTIPLE SIMULTANEOUS BI...

Method and System for Verifying Performance of an Array by Simulati...

DATA SHIFT CAPABILITY FOR SCANNABLE REGISTER