Vikram Kowshik

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and systems of cell-array programming for neural compute us...
- Patent number 11,961,570
- Issue date Apr 16, 2024
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature compensated common counter ADC method for neural compute
- Patent number 11,799,489
- Issue date Oct 24, 2023
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for analog in-memory compute for neural networks
- Patent number 11,687,765
- Issue date Jun 27, 2023
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of a smart decoding scheme for fast synchronou...
- Patent number 7,143,257
- Issue date Nov 28, 2006
- Atmel Corporation
- Vikram Kowshik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional register decoding system for multiple plane operation
- Patent number 7,099,226
- Issue date Aug 29, 2006
- Atmel Corporation
- Yolanda Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer having negative voltage level shifter
- Patent number 5,973,967
- Issue date Oct 26, 1999
- Programmable Microelectronics Corporation
- Chinh D. Nguyen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Nonvolatile PMOS two transistor memory cell and array
- Patent number 5,912,842
- Issue date Jun 15, 1999
- Programmable Microelectronics Corp.
- Shang-De Ted Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump
- Patent number 5,907,484
- Issue date May 25, 1999
- Programmable Microelectronics Corp.
- Vikram Kowshik
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Integrated program verify page buffer
- Patent number 5,903,497
- Issue date May 11, 1999
- Programmable Microelectronics Corporation
- Andy Teng-Feng Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive frequency compensation technique
- Patent number 5,889,440
- Issue date Mar 30, 1999
- Programmable Microelectronics Corp.
- Vikram Kowshik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sensing scheme for non-volatile memories
- Patent number 5,798,967
- Issue date Aug 25, 1998
- Programmable Microelectronics Corporation
- Vishal Sarin
- G11 - INFORMATION STORAGE
Information Patent Grant
Row decoder circuit for PMOS non-volatile memory cell which uses el...
- Patent number 5,796,656
- Issue date Aug 18, 1998
- Programmable Microelectronics Corporation
- Vikram Kowshik
- G11 - INFORMATION STORAGE
Information Patent Grant
PMOS non-volatile latch for storage of redundancy addresses
- Patent number 5,781,471
- Issue date Jul 14, 1998
- Programmable Microelectronics Corporation
- Vikram Kowshik
- G11 - INFORMATION STORAGE
Information Patent Grant
Row decoder circuit for PMOS non-volatile memory cell which uses ch...
- Patent number 5,777,926
- Issue date Jul 7, 1998
- Programmable Microelectronics Corporation
- Jayson Giai Trinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Switching circuit for controlled transition between high program an...
- Patent number 5,774,406
- Issue date Jun 30, 1998
- Programmable Microelectronic Corporation
- Vikram Kowshik
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative voltage level shift circuit
- Patent number 5,696,728
- Issue date Dec 9, 1997
- Programmable Microelectronics Corp.
- Andy Teng-Feng Yu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Programming pulse ramp control circuit
- Patent number 5,687,116
- Issue date Nov 11, 1997
- Programmable Microelectronics Corp.
- Vikram Kowshik
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump
- Patent number 5,625,544
- Issue date Apr 29, 1997
- Programmable Microelectronics Corp.
- Vikram Kowshik
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Two-transistor electrically-alterable switch employing hot electron...
- Patent number 5,625,211
- Issue date Apr 29, 1997
- Actel Corporation
- Vikram Kowshik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-transistor zero-power electrically-alterable non-volatile latch
- Patent number 5,587,603
- Issue date Dec 24, 1996
- Actel Corporation
- Vikram Kowshik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single-transistor electrically-alterable switch employing fowler no...
- Patent number 5,576,568
- Issue date Nov 19, 1996
- Actel Corporation
- Vikram Kowshik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable memory data protection scheme
- Patent number 4,975,878
- Issue date Dec 4, 1990
- National Semiconductor
- Sudhakar Boddu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential read access of serial memories with a user defined start...
- Patent number 4,873,671
- Issue date Oct 10, 1989
- National Semiconductor Corporation
- Vikram Kowshik
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power, electrically alterable, nonvolatile latch
- Patent number 4,858,185
- Issue date Aug 15, 1989
- National Semiconductor Corporation
- Vikram Kowshik
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND SYSTEMS FOR LOW NOISE OPERATION OF ANALOG IN MEMORY COM...
- Publication number 20240128978
- Publication date Apr 18, 2024
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF UTILIZING ANALOG TO DIGITAL CONVERTER (ADC)...
- Publication number 20240128979
- Publication date Apr 18, 2024
- vishal sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ANALOG IN-MEMORY COMPUTE FOR NEURAL NETWORKS
- Publication number 20210264243
- Publication date Aug 26, 2021
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEMPERATURE COMPENSATED COMMON COUNTER ADC METHOD FOR NEURAL COMPUTE
- Publication number 20210143828
- Publication date May 13, 2021
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF CELL-ARRAY PROGRAMMING FOR NEURAL COMPUTE US...
- Publication number 20210043264
- Publication date Feb 11, 2021
- Vishal Sarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Functional register decoding system for multiple plane operation
- Publication number 20050099857
- Publication date May 12, 2005
- Yolanda Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus of a smart decoding scheme for fast synchronou...
- Publication number 20050081011
- Publication date Apr 14, 2005
- Vikram Kowshik
- G06 - COMPUTING CALCULATING COUNTING

Vikram Kowshik

Person

Patents Grantslast 30 patents

Methods and systems of cell-array programming for neural compute us...

Temperature compensated common counter ADC method for neural compute

Method for analog in-memory compute for neural networks

Method and apparatus of a smart decoding scheme for fast synchronou...

Functional register decoding system for multiple plane operation

Page buffer having negative voltage level shifter

Nonvolatile PMOS two transistor memory cell and array

Charge pump

Integrated program verify page buffer

Adaptive frequency compensation technique

Sensing scheme for non-volatile memories

Row decoder circuit for PMOS non-volatile memory cell which uses el...

PMOS non-volatile latch for storage of redundancy addresses

Row decoder circuit for PMOS non-volatile memory cell which uses ch...

Switching circuit for controlled transition between high program an...

Negative voltage level shift circuit

Programming pulse ramp control circuit

Charge pump

Two-transistor electrically-alterable switch employing hot electron...

Two-transistor zero-power electrically-alterable non-volatile latch

Single-transistor electrically-alterable switch employing fowler no...

Programmable memory data protection scheme

Sequential read access of serial memories with a user defined start...

Zero power, electrically alterable, nonvolatile latch

Patents Applicationslast 30 patents

METHODS AND SYSTEMS FOR LOW NOISE OPERATION OF ANALOG IN MEMORY COM...

METHODS AND SYSTEMS OF UTILIZING ANALOG TO DIGITAL CONVERTER (ADC)...

METHOD FOR ANALOG IN-MEMORY COMPUTE FOR NEURAL NETWORKS

TEMPERATURE COMPENSATED COMMON COUNTER ADC METHOD FOR NEURAL COMPUTE

METHODS AND SYSTEMS OF CELL-ARRAY PROGRAMMING FOR NEURAL COMPUTE US...

Functional register decoding system for multiple plane operation

Method and apparatus of a smart decoding scheme for fast synchronou...