Vikram Santurkar

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 8,004,308
- Issue date Aug 23, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for serially transmitting on-chip termination control si...
- Patent number 7,999,568
- Issue date Aug 16, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,884,638
- Issue date Feb 8, 2011
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable multiple supply regions with switched pass gate level...
- Patent number 7,855,574
- Issue date Dec 21, 2010
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,719,309
- Issue date May 18, 2010
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,671,626
- Issue date Mar 2, 2010
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of reducing power in programmable logic devices using low v...
- Patent number 7,639,042
- Issue date Dec 29, 2009
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of reducing leakage current using sleep transistors in progr...
- Patent number 7,518,399
- Issue date Apr 14, 2009
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated parallel on-chip termination im...
- Patent number 7,443,193
- Issue date Oct 28, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,432,734
- Issue date Oct 7, 2008
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing calibrated on-chip termination impedance
- Patent number 7,423,450
- Issue date Sep 9, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for sensing temperature and automatic calibration on int...
- Patent number 7,410,293
- Issue date Aug 12, 2008
- Altera Corporation
- Vikram Santurkar
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for serially transmitting on-chip termination control si...
- Patent number 7,391,229
- Issue date Jun 24, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of reducing leakage current using sleep transistors in progr...
- Patent number 7,355,440
- Issue date Apr 8, 2008
- Altera Corporation
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of reducing power in programmable logic devices using low v...
- Patent number 7,262,634
- Issue date Aug 28, 2007
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,218,133
- Issue date May 15, 2007
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 7,161,381
- Issue date Jan 9, 2007
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 6,937,064
- Issue date Aug 30, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple size memories in a programmable logic device
- Patent number 6,720,796
- Issue date Apr 13, 2004
- Altera Corporation
- Srinivas Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Techniques for Providing Calibrated On-Chip Termination Impedance
- Publication number 20100225349
- Publication date Sep 9, 2010
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods of reducing power in programmable devices using low voltage...
- Publication number 20090146688
- Publication date Jun 11, 2009
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques for Providing Calibrated On-Chip Termination Impedance
- Publication number 20080297193
- Publication date Dec 4, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL...
- Publication number 20080094105
- Publication date Apr 24, 2008
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques For Providing Calibrated On-Chip Termination Impedance
- Publication number 20080061818
- Publication date Mar 13, 2008
- Altera Corporation
- Vikram Santurkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
- Publication number 20070252617
- Publication date Nov 1, 2007
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for low-power routing circuitry in programmab...
- Publication number 20070008004
- Publication date Jan 11, 2007
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods of reducing power in programmable logic devices using low v...
- Publication number 20060158220
- Publication date Jul 20, 2006
- Altra Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Versatile logic element and logic array block
- Publication number 20050127944
- Publication date Jun 16, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

Vikram Santurkar

Person

Patents Grantslast 30 patents

Techniques for providing calibrated on-chip termination impedance

Techniques for serially transmitting on-chip termination control si...

Techniques for providing calibrated on-chip termination impedance

Programmable multiple supply regions with switched pass gate level...

Techniques for providing calibrated on-chip termination impedance

Versatile logic element and logic array block

Methods of reducing power in programmable logic devices using low v...

Method of reducing leakage current using sleep transistors in progr...

Techniques for providing calibrated parallel on-chip termination im...

Versatile logic element and logic array block

Techniques for providing calibrated on-chip termination impedance

Techniques for sensing temperature and automatic calibration on int...

Techniques for serially transmitting on-chip termination control si...

Method of reducing leakage current using sleep transistors in progr...

Methods of reducing power in programmable logic devices using low v...

Versatile logic element and logic array block

Multiple size memories in a programmable logic device

Programmable logic device with redundant circuitry

Versatile logic element and logic array block

Multiple size memories in a programmable logic device

Patents Applicationslast 30 patents

Techniques for Providing Calibrated On-Chip Termination Impedance

Methods of reducing power in programmable devices using low voltage...

Techniques for Providing Calibrated On-Chip Termination Impedance

PROGRAMMABLE MULTIPLE SUPPLY REGIONS WITH SWITCHED PASS GATE LEVEL...

Techniques For Providing Calibrated On-Chip Termination Impedance

VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK

Apparatus and methods for low-power routing circuitry in programmab...

Methods of reducing power in programmable logic devices using low v...

Versatile logic element and logic array block

Programmable logic device with redundant circuitry