VIRENDRA R. JADHAV

Person

WAPPINGERS FALLS, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 11,244,917
- Issue date Feb 8, 2022
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 11,171,102
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 11,094,657
- Issue date Aug 17, 2021
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flat laminate, symmetrical test structures and method of use to gau...
- Patent number 10,699,972
- Issue date Jun 30, 2020
- International Business Machines Corporation
- William E. Bernier
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 10,403,590
- Issue date Sep 3, 2019
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 10,396,051
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal venting device with pressurized plenum
- Patent number 10,037,062
- Issue date Jul 31, 2018
- Microsoft Technology Licensing, LLC
- Siddharth Bhopte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flat laminate, symmetrical test structures and method of use to gau...
- Patent number 9,899,279
- Issue date Feb 20, 2018
- International Business Machines Corporation
- William E. Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 9,640,501
- Issue date May 2, 2017
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 9,472,520
- Issue date Oct 18, 2016
- International Business Machines Corporation
- Virendra R. Jadhav
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Determining magnitude of compressive loading
- Patent number 9,366,591
- Issue date Jun 14, 2016
- International Business Machines Corporation
- Paul F. Bodenweber
- G01 - MEASURING TESTING
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 9,111,816
- Issue date Aug 18, 2015
- International Business Machines Corporation
- Virendra R. Jadhav
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Flat laminate, symmetrical test structures and method of use to gau...
- Patent number 8,957,531
- Issue date Feb 17, 2015
- International Business Machines Corporation
- William E. Bernier
- G01 - MEASURING TESTING
Information Patent Grant
Determining magnitude of compressive loading
- Patent number 8,794,079
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Paul F. Bodenweber
- G01 - MEASURING TESTING
Information Patent Grant
Determining thermal interface material (TIM) thickness change
- Patent number 8,717,043
- Issue date May 6, 2014
- International Business Machines Corporation
- Paul F. Bodenweber
- G01 - MEASURING TESTING
Information Patent Grant
Achieving mechanical and thermal stability in a multi-chip package
- Patent number 8,421,217
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Jon A. Casey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer pillar for reduced stress interconnect and method of mak...
- Patent number 8,293,587
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Virendra R Jadhav
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Achieving mechanical and thermal stability in a multi-chip package
- Patent number 8,202,765
- Issue date Jun 19, 2012
- International Business Machines Corporation
- Jon A. Casey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip assembly with organic chip carrier having mushroom-plated...
- Patent number 7,952,207
- Issue date May 31, 2011
- International Business Machines Corporation
- Virendra R. Jadhav
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device assembly having a stress-relieving buffer layer
- Patent number 7,875,972
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for a pull test for controlled collapse chip c...
- Patent number 7,819,027
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Virendra R. Jadhav
- G01 - MEASURING TESTING
Information Patent Grant
Via offsetting to reduce stress under the first level interconnect...
- Patent number 7,812,438
- Issue date Oct 12, 2010
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic package with optimized circuitization pattern
- Patent number 7,088,008
- Issue date Aug 8, 2006
- International Business Machines Corporation
- David J. Alcoe
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stress reducing stiffener ring
- Patent number 6,703,704
- Issue date Mar 9, 2004
- International Business Machines Corporation
- David J. Alcoe
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20190326242
- Publication date Oct 24, 2019
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20190326243
- Publication date Oct 24, 2019
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20190157230
- Publication date May 23, 2019
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAU...
- Publication number 20180082912
- Publication date Mar 22, 2018
- International Business Machines Corporation
- William E. Bernier
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20170170135
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20170133338
- Publication date May 11, 2017
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20150054152
- Publication date Feb 26, 2015
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAU...
- Publication number 20150036716
- Publication date Feb 5, 2015
- International Business Machines Corporation
- William E. Bernier
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
DETERMINING MAGNITUDE OF COMPRESSIVE LOADING
- Publication number 20140331792
- Publication date Nov 13, 2014
- Paul F. Bodenweber
- G01 - MEASURING TESTING
Information Patent Application
DETERMINING MAGNITUDE OF COMPRESSIVE LOADING
- Publication number 20130112006
- Publication date May 9, 2013
- International Business Machines Corporation
- PAUL F. BODENWEBER
- G01 - MEASURING TESTING
Information Patent Application
Flat Laminate, Symmetrical Test Structures and Method of Use To Gau...
- Publication number 20130098176
- Publication date Apr 25, 2013
- International Business Machines Corporation
- William E. Bernier
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
DETERMINING THERMAL INTERFACE MATERIAL (TIM) THICKNESS CHANGE
- Publication number 20130027063
- Publication date Jan 31, 2013
- International Business Machines Corporation
- PAUL F. BODENWEBER
- G01 - MEASURING TESTING
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20120312447
- Publication date Dec 13, 2012
- International Business Machines Corporation
- Virendra R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20120181071
- Publication date Jul 19, 2012
- International Business Machines Corporation
- VIRENDRA R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN...
- Publication number 20120175766
- Publication date Jul 12, 2012
- International Business Machines Corporation
- Jon A. CASEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED...
- Publication number 20110195543
- Publication date Aug 11, 2011
- International Business Machines Corporation
- Virendra R. Jadhav
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER
- Publication number 20100327430
- Publication date Dec 30, 2010
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and Method of Achieving Mechanical and Thermal Stability in...
- Publication number 20100181665
- Publication date Jul 22, 2010
- International Business Machines Corporation
- Jon A. CASEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT...
- Publication number 20090174084
- Publication date Jul 9, 2009
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED...
- Publication number 20090146316
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Virendra R. Jadhav
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...
- Publication number 20090095502
- Publication date Apr 16, 2009
- International Business Machines Corporation
- VIRENDRA R. JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR A PULL TEST FOR CONTROLLED COLLAPSE CHIP C...
- Publication number 20080313879
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Virendra R. Jadhav
- G01 - MEASURING TESTING
Information Patent Application
STRUCTURE FOR CONTROLLED COLLAPSE CHIP CONNECTION WITH A CAPTURED P...
- Publication number 20080142968
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Virendra R. Jadhav
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip carrier with optimized circuitization pattern
- Publication number 20040183211
- Publication date Sep 23, 2004
- International Business Machines Corporation
- David J. Alcoe
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

VIRENDRA R. JADHAV

Person

Patents Grantslast 30 patents

Multilayer pillar for reduced stress interconnect and method of mak...

Multilayer pillar for reduced stress interconnect and method of mak...

Multilayer pillar for reduced stress interconnect and method of mak...

Flat laminate, symmetrical test structures and method of use to gau...

Multilayer pillar for reduced stress interconnect and method of mak...

Multilayer pillar for reduced stress interconnect and method of mak...

Thermal venting device with pressurized plenum

Flat laminate, symmetrical test structures and method of use to gau...

Multilayer pillar for reduced stress interconnect and method of mak...

Multilayer pillar for reduced stress interconnect and method of mak...

Determining magnitude of compressive loading

Multilayer pillar for reduced stress interconnect and method of mak...

Flat laminate, symmetrical test structures and method of use to gau...

Determining magnitude of compressive loading

Determining thermal interface material (TIM) thickness change

Achieving mechanical and thermal stability in a multi-chip package

Multilayer pillar for reduced stress interconnect and method of mak...

Achieving mechanical and thermal stability in a multi-chip package

Flip-chip assembly with organic chip carrier having mushroom-plated...

Semiconductor device assembly having a stress-relieving buffer layer

Method and structure for a pull test for controlled collapse chip c...

Via offsetting to reduce stress under the first level interconnect...

Electronic package with optimized circuitization pattern

Stress reducing stiffener ring

Patents Applicationslast 30 patents

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAU...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAU...

DETERMINING MAGNITUDE OF COMPRESSIVE LOADING

DETERMINING MAGNITUDE OF COMPRESSIVE LOADING

Flat Laminate, Symmetrical Test Structures and Method of Use To Gau...

DETERMINING THERMAL INTERFACE MATERIAL (TIM) THICKNESS CHANGE

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN...

FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED...

SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER

System and Method of Achieving Mechanical and Thermal Stability in...

VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT...

FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED...

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAK...

METHOD AND STRUCTURE FOR A PULL TEST FOR CONTROLLED COLLAPSE CHIP C...

STRUCTURE FOR CONTROLLED COLLAPSE CHIP CONNECTION WITH A CAPTURED P...

Chip carrier with optimized circuitization pattern