Vivek THIRTHA

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-all-around integrated circuit structures having fin stack isol...
- Patent number 11,594,637
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DEPOP using cyclic selective spacer etch
- Patent number 11,569,370
- Issue date Jan 31, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF CONTROLLING METAL GATE HEIGHT AND SELECTIVE SPACER FORMATION
- Publication number 20250220944
- Publication date Jul 3, 2025
- Intel Corporation
- Shao Ming Koh
Information Patent Application
GATE-ALL-AROUND DEVICES WITH DIFFERENT GATE LENGTHS
- Publication number 20250220969
- Publication date Jul 3, 2025
- Intel Corporation
- Shao Ming Koh
Information Patent Application
SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GA...
- Publication number 20240071831
- Publication date Feb 29, 2024
- Intel Corporation
- Chang Wan Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-SITU MULTI-LAYER DIELECTRIC FILMS FOR APPLICATION AS GATE SPACER...
- Publication number 20240006512
- Publication date Jan 4, 2024
- Intel Corporation
- Walter CASPER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...
- Publication number 20230197818
- Publication date Jun 22, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20230163215
- Publication date May 25, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...
- Publication number 20220416042
- Publication date Dec 29, 2022
- Intel Corporation
- William HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR...
- Publication number 20220416044
- Publication date Dec 29, 2022
- Intel Corporation
- Nitesh KUMAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...
- Publication number 20220416041
- Publication date Dec 29, 2022
- Intel Corporation
- Mohammad HASAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20210305430
- Publication date Sep 30, 2021
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEPOP USING CYCLIC SELECTIVE SPACER ETCH
- Publication number 20200411661
- Publication date Dec 31, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS

Vivek THIRTHA

Person

Patents Grantslast 30 patents

Gate-all-around integrated circuit structures having fin stack isol...

DEPOP using cyclic selective spacer etch

Patents Applicationslast 30 patents

METHOD OF CONTROLLING METAL GATE HEIGHT AND SELECTIVE SPACER FORMATION

GATE-ALL-AROUND DEVICES WITH DIFFERENT GATE LENGTHS

SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GA...

IN-SITU MULTI-LAYER DIELECTRIC FILMS FOR APPLICATION AS GATE SPACER...

FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...

LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR...

NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

DEPOP USING CYCLIC SELECTIVE SPACER ETCH