Patent Application
20240071831
The present disclosure relates to integrated circuits, and more particularly, to processes for formation of source and drain regions in laterally adjacent devices.
Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow between the source and drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device; and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. MOSFETs may also be known as metal-insulator-semiconductor FETs (MISFETSs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) devices to implement logic gates and other digital circuits.
A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations includes three different planer regions of the fin (e.g., top and two sides), such a FinFET design is sometimes referred to as a tri-gate transistor. A gate-all-around (GAA) transistor (sometimes referred to as a nanoribbon or nanowire transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region, one or more channel bodies such as nanoribbons or nanowires extend between the source and the drain regions. In GAA transistors, the gate material wraps around each nanoribbon (hence, gate-all-around). There are various non-trivial issues associated with formation of GAA transistor devices.
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. Likewise, while the thickness of a given first layer may appear to be similar in thickness to a second layer, in actuality that first layer may be much thinner or thicker than the second layer; same goes for other layer or feature dimensions.
Techniques are provided herein to form an integrated circuit comprising a first device laterally adjacent to a second device, where the first device is one of a p-channel metal-oxide semiconductor (PMOS) device or a n-channel metal-oxide semiconductor (NMOS) device, and the second device is the other of the PMOS device or the NMOS device. For example, first inner spacers, a first source region, and a first drain region of the first device are formed, followed by formation of second inner spacers, a second source region, and a second drain region of the second device. For example, when the first inner spacers, the first source region, and the first drain region of the first device are being formed, the second device is protected (e.g., masked) by a mask. After formation of the first inner spacers, the first source region, and the first drain region of the first device is complete, the second inner spacers, the second source region, and the second drain region of the second device are formed, while now the first device is protected by a layer of dielectric material (note that the layer of dielectric material may not, or may, be later removed). Masking the second device while forming the above discussed components of first device, and similarly, protecting the first device (e.g., using the layer of dielectric material) while forming the above discussed components of second device ensures, for example, that exposed tip or end regions of the channel materials (e.g., which are exposed through the source or drain trenches) are not contaminated by any foreign material, as will be discussed in further detail herein below.
In one embodiment, an integrated circuit structure comprises a first device laterally adjacent to a second device. The first device comprises (i) a first source or drain region, (ii) a first body comprising semiconductor material laterally extending from the first source or drain region, (iii) a first gate structure wrapping around a section of the first body, and (v) a first inner spacer between the first source or drain region and the first gate structure. The second device comprises (i) a second source or drain region, (ii) a second body comprising semiconductor material laterally extending from the second source or drain region, (iii) a second gate structure wrapping around a section of the second body, and (v) a second inner spacer between the second source or drain region and the second gate structure. The first source or drain region has a first width in a direction parallel to the first body, the second source or drain region has a second width in the direction parallel to the first body, the first inner spacer has a third width in the direction parallel to the first body, and the second inner spacer has a fourth width in the direction parallel to the first body. In an example, the first width is different from the second width by at least 1 nm. Additionally, or alternatively, the third width is different from the fourth with by at least 1 nm. In an example, the first device is one of a PMOS device or an NMOS device, and the second device is the other of the PMOS device or the NMOS device. For example, the first device and the second device are arranged in a complementary metal oxide semiconductor (CMOS) architecture.
In another embodiment, an integrated circuit structure comprises a first device laterally adjacent to a second device. The first device comprises (i) a first source or drain region and a corresponding first source or drain contact, (ii) a first gate structure and a corresponding first gate contact, (iii) a first layer comprising a first dielectric material and an adjacent second layer comprising a second dielectric material, wherein the first layer and the second layer are laterally between the first gate contact and the first source or drain contact, and (iv) a first inner spacer laterally between the first source or drain region and the first gate structure. In an example, the second device comprises (i) a second source or drain region and a corresponding second source or drain contact, (ii) a second gate structure and a corresponding second gate contact, (iii) a third layer comprising the first dielectric material and an adjacent fourth layer comprising the second dielectric material, wherein the third layer and the fourth layer are laterally between the second gate contact and the second source or drain contact, and (iv) a second inner spacer laterally between the second source or drain region and the second gate structure. In an example, the first inner spacer is below the first layer and not below the second layer. In an example, the second inner spacer is below the fourth layer. In an example, the second inner spacer is also below the third layer. In an example, a first interface is between the first and second layers, and a second interface is between the third and fourth layers.
In yet another embodiment, a method of forming laterally adjacent first and second devices includes forming laterally adjacent first fin and second fin. Each of the first and second fins comprises alternate layers of channel materials and sacrificial materials. In an example, the method further comprises patterning the first fin, to form a first source or drain trench adjacent to the first fin, while protecting a laterally adjacent second fin using a mask and refraining from forming any source or drain trench adjacent to the second fin. In an example, the method further comprises recessing end portion of the sacrificial materials of the first fin through the first source or drain trench, and forming a first inner spacer adjacent the first fin. In an example, the method further comprises forming a first source or drain region within the first source or drain trench. In an example, the method further comprises subsequent to forming the first source or drain region, patterning the second fin, to form a second source or drain trench adjacent to the second fin. In an example, the method further comprises recessing end portion of the sacrificial materials of the second fin through the second source or drain trench, and forming a second inner spacer adjacent the second fin. In an example, the method further comprises forming a second source or drain region within the second source or drain trench. Numerous configurations and variations will be apparent in light of this disclosure.
As mentioned herein above, there are various non-trivial issues associated with formation of GAA transistor devices. For example, assume a first device laterally adjacent to a second device, where the first device is one of a PMOS GAA device or an NMOS GAA device, and the second device is the other of the PMOS GAA device or the NMOS GAA device. In an example, to form the source and drain regions of the two devices, fins of both devices are selectively recessed, e.g., to form source and drain trenches for both devices. Subsequently, inner spacers are formed adjacent to the source and drain trenches, such that tips of channel materials are exposed through the inner spacers. Note that in an example, the PMOS device source and drain regions may be compositionally different from the NMOS device source and drain regions. To prevent PMOS source and drain region epitaxial growth on a NMOS device and/or to prevent NMOS source and drain region epitaxial growth on a PMOS device, after formation of the inner spacers in the laterally adjacent NMOS and PMOS devices, a layer or film comprising dielectric material is deposited within the source or drain trenches of both devices. Note that the film comprising dielectric material is in contact with the tips of channel materials (e.g., which will later be released to form the nanoribbons) of both devices. Subsequently, the thin film of one of the two devices (e.g., the first device) is removed and the epitaxial source and drain regions of the first device are formed. Subsequently, the thin film of the other of the two devices (e.g., the second device) is removed and the epitaxial source and drain regions of the second device are formed. This way, PMOS source and drain regions cannot grow on the NMOS device, and NMOS source and drain regions cannot grow on the PMOS device. However, even though the film comprising dielectric material is removed, residues or remnants of the film may remain on the tips of the nanoribbons (e.g., channel regions) of the two devices.
Accordingly, techniques are provided herein to form an IC that includes a first device laterally adjacent to a second device, where first inner spacers, a first source region, and a first drain region of the first device are initially formed, followed by formation of second inner spacers, a second source region, and a second drain region of the second device. In an example, the first device is one of a PMOS GAA device or an NMOS GAA device, and the second device is the other of the PMOS GAA device or the NMOS GAA device. Note that an example of the channel region in a GAA device includes nanoribbons. As will be appreciated in light of this disclosure, reference to nanoribbons as channel regions is also intended to include other gate-all-around or multi-gate channel regions, such as nanowires, nanosheets, and other such semiconductor bodies around which a gate structure can wrap. To this end, the use of a specific channel region configuration (e.g., nanoribbon) is not intended to limit the present description to that specific channel configuration. Rather, the techniques provided herein can benefit any number of channel configurations, whether those bodies be nanowires, nanoribbons, nanosheets or some other body around which a gate structure can at least partially wrap (such as the semiconductor bodies of a forksheet device or a fin-based device).
Continuing with the above discussion regarding formation of the laterally adjacent first and second devices, initially two adjacent fins are formed, a left fin for forming a left device and a right fin for forming a right device. Each of the fins comprise alternating layers of sacrificial material and channel material. One or more dummy gates are formed above each of the left and right fins, and a first layer comprising dielectric material are deposited above the resultant structure (see
A mask (e.g., a hard mask, such as a carbon hard mask) is formed on a fin, e.g., on the right fin, the dummy gates above the right fin, and the first layer above the right fin (e.g., see
Note that the notations left and right devices (or left and right fins) are used herein as mere examples, e.g., for ease of identification, and is not intended to be limiting. However, the left and right devices can be interchanged, such that the above discussed mask is initially formed above the left fin and the left device is initially processed, prior to the right fin.
Now the left fin, which is not covered by the mask, is selectively recessed (e.g., portions of the left fin, which are not covered by the dummy gates, are recessed and removed), e.g., see
Subsequently, a second layer of dielectric material is deposited on the resultant structure, e.g., see
In an example, a third layer of dielectric material may now be deposited over the structure (see
Thus, as seen above, the inner spacers and the source and drain regions of the left device are formed, followed by formation of the inner spacers and the source and drain regions of the right device. For example, when these components of the left device are being formed, the right device is protected (e.g., masked) by a mask. Subsequently, the inner spacers and the source and drain regions of the right device are formed, while now the left device is protected by the above discussed second layer of dielectric material (note that the layer of dielectric material may not, or may, be later removed). Masking the right device while forming the above discussed components of left device, and similarly, protecting the left device (e.g., using the second layer of dielectric material) while forming the above discussed components of right device eliminates the need of using the thin film to cover the exposed tips of the channel materials, as discussed herein above. Accordingly, the techniques provided herein for forming the source or drain regions of the left and right devices avoid the above discussed contamination issues, thereby improving performance of the first and second devices.
Note that the second layer of dielectric material hasn't been deposited yet, e.g., when the inner spacers of the left device are being formed. In contrast, both the first and second layers of dielectric material have been deposited, e.g., when the inner spacers of the right device are being formed. Accordingly, in an example, as will also be discussed in further detail herein below, the inner spacers of the left device are formed below the first layer of dielectric material (and not below the second layer of dielectric material), while the inner spacers of the right device are formed below the second layer of dielectric material and may also be formed below the first layer of dielectric material.
In an example and as will be discussed herein below in further detail, a horizontal width of the inner spacers of the right device may be more than a horizontal width of the inner spacers of the left device, e.g., by at least 1 nm, or at least 1.5 nm, or at least 2 nm, or at least 2.5 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm. However, in some other embodiments, the inner spacers of the left and right devices may be substantially similar, e.g., within 1 nm of each other. Various widths discussed herein are in a direction parallel to a length of the nanoribbons.
In an example, due to the formation process discussed herein above and also discussed in further detail herein below, a width of the source or drain regions of the left device may be more than a width of the source or drain regions of the right device, e.g., by at least 1 nm, or at least 1.5 nm, or at least 2 nm, or at least 2.5 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm. However, in some other embodiments, the source or drain regions of the left and right devices may be substantially similar, e.g., within 1 nm of each other. Various widths discussed herein are in a direction parallel to a length of the nanoribbons. For example, a width w1 of the source or drain trenches of the left device is defined by opposing sidewalls of the first layer of dielectric material (see
Note that the above discussed first, second, and third layers of dielectric materials are deposited using different deposition processes. Accordingly, there may be an interface (e.g., seam or grain boundary) between two adjacent sections of the first and second layers, and/or there may be an interface (e.g., seam or grain boundary) between two adjacent sections of the second and third layers, in an example.
The use of “group IV semiconductor material” (or “group IV material” or generally, “IV”) herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and so forth. The use of “group III-V semiconductor material” (or “group III-V material” or generally, “III-V”) herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example.
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the material has an element that is not in the other material.
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools be used to detect a first device laterally adjacent to a second device, wherein a first layer and a second layer of dielectric materials are between a gate contact and a source or drain contact of each of the devices, and wherein inner spacers of one of the devices (e.g., the first device) are formed below the first layer of dielectric material (and not below the second layer of dielectric material), while the inner spacers of the other one of the devices (e.g., the second device) are formed below the second layer of dielectric material and may also be formed below the first layer of dielectric material. In an example, an interface (such as a seam or grain boundary) is between an adjacent section of the first layer and an adjacent section of the second layer of dielectric materials. In an example, a horizontal width of the inner spacers of the first device and a horizontal width of the inner spacers of the second device differ by at least 1 nm, or at least 1.5 nm, or at least 2 nm, or at least 2.5 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm. In an example, a horizontal width of a source or drain region of the first device and a horizontal width of the source or drain region of the second device differ by at least 1 nm, or at least 1.5 nm, or at least 2 nm, or at least 2.5 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm. Various widths discussed herein are in a direction parallel to a length of a channel region of either of the first or second devices. Numerous configurations and variations will be apparent in light of this disclosure.
Architecture
As can be seen, the cross-section of
The device configuration includes laterally adjacent devices 101 and 140. There may be an isolation region, one or more other devices, and/or dielectric material (such as interlayer dielectric material or ILD) between the two laterally adjacent devices 101, 140. In an example, one of the two devices 101, 140 is a PMOS device and the other of the two devices 101, 140 is an NMOS device. In an example, the devices 101, 140 may be arranged in a complementary metal-oxide semiconductor (CMOS) configuration. Note the devices 101, 140 being identified as a left device and a right device, respectively, is merely for the sake of identifying the two devices, such delineation does not necessarily indicate that that the device 101 has to be always on the left of the device 140 (e.g., the device 140 may also be on a left side of the device 101 in an example).
In the example of
In the example of
Although not illustrated, in an example, each of the source or drain regions may comprise a relatively lightly doped nucleation region and a relatively heavily doped main region. Numerous source and drain configurations can be used, and the present disclosure is not intended to be limited to any particular ones. In some example embodiments, the various source and drain regions are epitaxial source and drain regions that are provided after the relevant portion of the fin or fin structure was isolated and etched away or otherwise removed. In other embodiments, the source/drain regions may be doped portions of the fin structure or substrate, rather than epi regions. In some embodiments using an etch and replace process, the epi source and drain regions are faceted and overgrown from a trench within insulator material (e.g., shallow trench isolation, or inner spacer that deposits on the sides of the fin structure in the source and drain locations), and the corresponding source or drain contact structure lands on that faceted portion. Alternatively, in other embodiments, the faceted portion of epi source and drain regions can be removed (e.g., via chemical mechanical planarization, or CMP), and the corresponding source or drain contact structure lands on that planarized portion.
The source and drain regions can be any suitable semiconductor material and may include any dopant scheme. In an example, source and drain regions can be PMOS source and drain regions that include, for example, group IV semiconductor materials such as silicon, germanium, SiGe, germanium tin (GeSn), SiGe alloyed with carbon (SiGe:C). Example p-type dopants include boron, gallium, indium, and aluminum. Source and drain regions can be NMOS source and drain regions that include, for example, silicon or group III-V semiconductor materials such as two or more of indium, aluminum, arsenic, phosphorus, gallium, and antimony, with some example compounds including but not limited to indium aluminum arsenide, indium arsenide phosphide, indium gallium arsenide, indium gallium arsenide phosphide, gallium antimonide, gallium aluminum antimonide, indium gallium antimonide, or indium gallium phosphide antimonide. In one specific embodiment, PMOS source and drain regions are boron-doped SiGe, and NMOS source and drain regions are phosphorus-doped silicon. In a more general sense, the source and drain regions can be any semiconductor material suitable for a given application.
In some cases, the epi source and drain regions may include a multilayer structure, such as a germanium cap on a SiGe body, or a germanium body and a carbon-containing SiGe spacer or liner between the corresponding channel region and that germanium body. In any such cases, a portion of the epi source and drain regions may have a component that is graded in concentration, such as a graded germanium concentration to facilitate lattice matching, or a graded dopant concentration to facilitate low contact resistance. Any number of source and drain configurations can be used as will be appreciated, and the present disclosure is not intended to be limited to any particular such configurations.
As discussed, the devices 101 and 140 are laterally adjacent. For example, a right edge of the drain region 104b of the device 101 and a left edge of the source region 106a of the device 140 is laterally separated by a distance that is in the range of 15-1000 nm, or in a subrange of 15-800 nm, 15-600 nm, 15-400 nm, 15-200 nm, 15-100 nm, 100-1000 nm, 100-800 nm, 100-500 nm, 100-200 nm, 200-500 nm, or another appropriate subrange thereof.
Referring to the device 101, in one embodiment, one or more gate structures 122 of the device 101 wraps around each of the nanoribbons 103a in the corresponding channel region. Note that a gate structure 122 of the device 101 is labelled within an expanded view of a section 149a of the device 101. Inner spacers 134a isolate the gate structures 122 from contacting the source region 104a and the drain region 104b. Thus, an inner spacer 134a is laterally between a gate structure 122 and a corresponding one of a source or drain region 104a, 104b. In other embodiments, there may be other insulator layers (e.g., interlayer dielectric) that prevent such contact, whether in addition to the gate spaces 134a, or in place of the inner spacers 134a. In an example, conductive gate contacts 125a, 125b, and 125c provide contacts to respective three gate structures of the device 101.
In one embodiment, each of gate structures 172 of the device 140 wraps around each of the nanoribbons 103b in the corresponding channel region. Note that a gate structure 172 of the device 140 is labelled within an expanded view of a section 149b of the device 140. Inner spacers 134b isolate the gate structures 172 from contacting the source region 106a and the drain region 106b. Thus, an inner spacer 134b is laterally between a gate structure 172 and a corresponding one of a source or drain region 106a, 106b. In other embodiments, there may be other insulator layers (e.g., interlayer dielectric) that prevent such contact, whether in addition to the gate spaces 134b, or in place of the inner spacers 134b. In an example, conductive gate contacts 125d, 125e, and 125f provide contacts to respective three gate structures 172 of the device 140.
Each of gate structures 122, 172 can be formed via gate-first or gate-last processing, and may include any number of suitable gate materials and configurations. In an embodiment, each of the gate structures 122, 172 includes a corresponding gate electrode and a gate dielectric 120 between the gate electrode and the corresponding nanoribbons 103, where the gate dielectric 120 is illustrated in the expanded views of the sections 149a and 149b of the devices 101, 140.
In one example the inner spacers 134 may be considered part of the gate structure, whereas in another example the inner spacers 134 may be considered external to the gate structure. Each of the gate structures 122 of the left device 101 comprises a corresponding gate electrode 105a and corresponding dielectric material 120. Note that the dielectric material 120 of the gate structures 122 is illustrated in an expanded view of the section 149a of the device 101. Each of the gate structures 172 of the right device 140 comprises a corresponding gate electrode 105b and corresponding dielectric material 120. Note that the dielectric material 120 of the gate structures 172 is illustrated in an expanded view of a section 149b of the device 140.
The gate dielectric material 120 warps around middle section of individual nanoribbons 103 (note that end sections of individual nanoribbons 103 are wrapped around by the inner spacers 134). The gate dielectric material 120 is between individual nanoribbons 103 and corresponding gate electrode, as illustrated. In an example, due to conformal deposition of the gate dielectric material 120, the gate dielectric material 120 may also be on inner sidewalls of the inner spacers 134, as illustrated in the expanded views of the sections 149a, 149b.
The gate dielectric 120 may include a single material layer or multiple stacked material layers. The gate dielectric 120 may include, for example, any suitable oxide (such as silicon dioxide), high-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. The high-k dielectric material (e.g., hafnium oxide) may be doped with an element to affect the threshold voltage of the given semiconductor device. According to some embodiments, the doping element used in gate dielectric 120 is lanthanum. In some embodiments, the gate dielectric can be annealed to improve its quality when high-k dielectric material is used. In some embodiments, the gate dielectric 120 includes a first layer (e.g., native oxide of nanoribbons, such as silicon dioxide or germanium oxide or SiGe-oxide) on the nanoribbons, and a second layer of high-k dielectric (e.g., hafnium oxide) on the first layer.
In an example, the gate electrode 105a of the device 101 and the gate electrode 105b of the device 140 may include any sufficiently conductive material, such as a metal, metal alloy, or doped polysilicon. The gate electrodes may include a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, cobalt, molybdenum, titanium nitride, or tantalum nitride, for example.
In one embodiment, one or more work function materials (not illustrated in
The semiconductor bodies 103a, 103b, which in this case are nanoribbons, can be any number of semiconductor materials, such as group IV material (e.g., silicon, germanium, or SiGe) or group III-V materials (e.g., indium gallium arsenide). In other embodiments, the semiconductor bodies 103 may be fins on which the corresponding gate structures are formed to provide double-gate or tri-gate configurations (as opposed to gate-all-around configurations with nanoribbons or wires). The semiconductor bodies 103 may be lightly doped, or undoped, and may be shaped or sculpted during the gate formation process, according to some embodiments. In some cases, semiconductor bodies 103 may be a multilayer structure, such as a SiGe body cladded with germanium, or a silicon body cladded with SiGe. Any number of channel configurations can be used.
As illustrated in
In an example, individual ones of the source or drain contacts 144, 145 comprises conductive material, such as one or more metals or an alloy thereof. Example materials of the source or drain contacts include one or more metals such as titanium (Ti), vanadium (V), zirconium (Zr), Niobium (Nb), iron (Fe), cobalt (Co), nickel (Ni), ruthenium (Ru), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), rhodium (Rh), palladium (Pd), hafnium (Hf), tantalum (Ta), tungsten (W), molybdenum (Mo), and/or carbides, borides, silicides, and/or germanides thereof (e.g., in dilute and/or stochiometric form).
In one embodiment, a plurality of layers comprising dielectric materials separate a source or drain contact from an adjacent gate contact. For example, layers 132, 136, 150 comprising dielectric materials are adjacent to each of the gate contacts 125a, . . . , 125f, and separate a gate contact 125 from an adjacent source or drain contact. For example, each layer 132 of dielectric material is adjacent to a corresponding gate contact 125. Each layer 132 is laterally between a corresponding gate contact 125 and a corresponding layer 136. For example, the layer 132 separates the corresponding gate contact 125 from the layer 136. In an example, at least a section of a layer 150 is between a corresponding section of the layer 136 and a source or drain contact 144 or 145. Thus, three layers 132, 136, 150 of dielectric materials separate a source or drain contact from an adjacent gate contact, as illustrated.
In an example, the dielectric materials of layers 132 and 136 may be compositionally and/or elementally the same or different. Similarly, in an example, dielectric materials of layers 136 and 150 may be compositionally and/or elementally the same or different. In an example, each of the layers 132, 136, and 150 are formed using different process flows, e.g., formed at different times during the processes to form the structure 100, as will be discussed herein below with respect to
In an example, each of the layers 132, 136, and 150 comprises an appropriate dielectric material, such as silicon oxide, silicon nitride, and/or another appropriate nitride, oxide, carbide, oxycarbide, oxynitride, or oxycarbonitride. As discussed, the dielectric materials of layers 132, 136, and/or 150 may be compositionally and/or elementally the same or different. As also discussed, irrespective of the composition of the dielectric materials of the layers 132, 136, and 150, an interface (e.g., a seam or grain boundary) is present between adjacent sections of the layers 132 and 136, and/or between adjacent sections of the layers 136 and 150.
In an example, a width of the source and/or drain regions 104a, 104b of the device 101 is about w1, and a width of the source and/or drain regions 106a, 106b of the device 140 is about w2, where the widths w1, w2 are measured in a direction parallel to a direction in which the nanoribbons 103 extend, such as in the X axis direction in
In an example, the widths w1 and w2 are substantially the same, e.g., within 1 nm, or 1.5 nm, or 2 nm of each other. In another example and as will be discussed herein below in further detail, the widths w1 and w2 may be different from each other by at least 1 nm, or at least 1.5 nm, or at least 2 nm, or at least 2.5 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm. For example, as will be discussed in further detail herein below with respect to
In an example, each inner spacer 134a of the device 101 is formed below a corresponding layer 132, and no portion of the inner spacer 134a is below the layer 136. For example, as will be discussed herein below in further detail with respect to
In contrast, each inner spacer 134b of the device 140 is formed below a corresponding layer 136, and some portion of the inner spacer 134b may also be below the corresponding layer 132. For example, as will be discussed herein below in further detail with respect to
In an example, a side wall of an inner spacer 134a and/or 134b is aligned with a side wall of a corresponding gate electrode 125. As an example, a left sidewall of the inner spacer 134a on an immediate left of the source region 104a is substantially aligned (e.g., substantially coplanar) with a right sidewall of the gate electrode 125a. In another example, a right sidewall of the inner spacer 134b on an immediate right of the source region 106a is substantially aligned (e.g., substantially coplanar) with a left sidewall of the gate electrode 125e.
In an example, a width of the inner spacer 134a of the device 101 is about w3, and a width of the inner spacer 134b of the device 140 is about w4, where the widths w3 and w4 are measured in a direction parallel to a direction in which the nanoribbons 103 extend, such as in the X axis direction in
In
As illustrated in
In an example, a bottom surface of the source or drain regions 104a, 104b of the device 101 may not be coplanar with a bottom surface of the source or drain regions 106a, 106b of the device 140. For example, as will be discussed herein below in further details, trenches for the source or drain regions 104a, 104b of the device 101 are formed using first one or more processes (e.g., see
Also illustrated in
Referring to
The method 200 then proceeds from 204 to 208, where a mask 302 (e.g., a hard mask, such as a carbon hard mask) is patterned on the fin 301b, the dummy gates 325d, 325e, 325f, and the layer 132 thereon, as illustrated in
The method 200 then proceeds from 208 to 212, where the left fin 301a (e.g., which is not covered by the mask 302) is patterned, to form source and drain trenches 307a, 307b within the fin 301a, while the mask 302 protects the right fin 301b from being patterned, as illustrated in
The method 200 then proceeds from 212 to 216, where end portions of the sacrificial materials 303a of the left device 101 are recessed through the source and drain trenches 307a, 307b, as illustrated in
In an example, as the fin 301b of the right device 140 is still covered by the mask 302, the process 216 doesn't affect the fin 301b of the right device 140. In another example, the mask 302 may be removed prior to, or during the process 216, and the layer 132 on the right fin 301b may continue to protect the sacrificial material 303b and/or the channel material 103b of the right fin 301b from being etched during the process 216.
The method 200 then proceeds from 216 to 220, where mask 302 is removed (e.g., etched), as illustrated in FIG. 3D1. Note that although the mask 302 is removed in the process 220, the mask 302 could have been removed during an earlier process as well, e.g., between processes 212 and 216. Also, at 220, inner spacers 134a are formed within the recesses 308 of the left device 101, as illustrated in
The method 200 then proceeds from 220 to 224, where the source and drain regions 104a, 104b of the left device 101 are formed, as illustrated in
The method 200 then proceeds from 224 to 228, where the layer 136 is deposited on the resultant structure, as illustrated in
Comparing width w1 of
However, in another example, layer 132 in
Also at 228, a mask 302a is patterned on the left device 101, as illustrated in
The method 200 then proceeds from 228 to 232, where the fin 301b of the right device 140 (e.g., which is not covered by the mask 302a) is patterned, to form source and drain trenches 309a, 309b, as illustrated in
The method 200 then proceeds from 232 of
The method 200 then proceeds from 236 to 240, where inner spacers 134b are formed within the recesses 310 of the right device 140, as illustrated in
The method 200 then proceeds from 240 to 244, where source and drain regions 106a, 106b of the right device 140 are formed, as illustrated in
Note that each of the source and drain trenches 309a, 309b had the width w2, which is discussed herein above with respect to
The method 200 then proceeds from 244 to 248, where layer 150 comprising dielectric material layer 150 is deposited (e.g., blanket deposited) over the structure 100, e.g., using an appropriate deposition technique, such as CVD, PVD, ALD, VPE, MBE, or LPE, for example, as illustrated in
The method 200 then proceeds from 248 to 252, where for both devices 101, 140, top portions of the layers 150, 136, 132 are recessed, so as to expose the dummy gates 325, as illustrated in
Furthermore, also at 252, the dummy gate material 325 are removed (see
The method 200 then proceeds from 252 to 256, where final gate structures 122 for device 101 and final gate structures 172 for device 140 are formed, as illustrated in
The method 200 then proceeds from 256 to 260, where gate contacts 125 and various source and drain contacts 144, 145 for devices 101, 140 are formed, as illustrated in
The method 200 then proceeds from 260 to 264, where a general integrated circuit (IC) is completed, as desired, in accordance with some embodiments. Such additional processing to complete an IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers, and/or to interconnect the transistor devices formed, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure.
Note that the processes in method 200 are shown in a particular order for ease of description. However, one or more of the processes may be performed in a different order or may not be performed at all (and thus be optional), in accordance with some embodiments. Numerous variations on method 200 and the techniques described herein will be apparent in light of this disclosure.
Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
The foregoing description of example embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.
