Walter R. Steiner

Person

Flagler Beach, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
State handling in a tiled architecture
- Patent number 10,282,803
- Issue date May 7, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed tiled caching
- Patent number 10,032,243
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiresolution consistent rasterization
- Patent number 9,947,084
- Issue date Apr 17, 2018
- NVIDIA Corporation
- Eric B. Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for improving performance in a tile based architecture
- Patent number 9,792,122
- Issue date Oct 17, 2017
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consistent vertex snapping for variable resolution rendering
- Patent number 9,747,661
- Issue date Aug 29, 2017
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conservative rasterization of primitives using an error term
- Patent number 9,633,469
- Issue date Apr 25, 2017
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reducing a polygon bounding box
- Patent number 9,633,458
- Issue date Apr 25, 2017
- NVIDIA Corporation
- Walter R. Steiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early sample evaluation during coarse rasterization
- Patent number 9,495,781
- Issue date Nov 15, 2016
- NVIDIA Corporation
- Eric Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed tiled caching
- Patent number 9,483,270
- Issue date Nov 1, 2016
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consistent vertex snapping for variable resolution rendering
- Patent number 9,478,066
- Issue date Oct 25, 2016
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient round point rasterization
- Patent number 9,311,733
- Issue date Apr 12, 2016
- NVIDIA Corporation
- Walter R. Steiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing a graphics rendering pipeline using early Z-mode
- Patent number 8,933,933
- Issue date Jan 13, 2015
- NVIDIA Corporation
- Mark J. French
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for parallel fine rasterization in a raster stage of a graph...
- Patent number 8,928,676
- Issue date Jan 6, 2015
- NVIDIA Corporation
- Walter R. Steiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for deferred coverage mask generation in a raster...
- Patent number 8,537,168
- Issue date Sep 17, 2013
- NVIDIA Corporation
- Walter R. Steiner
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING
- Publication number 20170046812
- Publication date Feb 16, 2017
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT ROUND POINT RASTERIZATION
- Publication number 20140267382
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Walter R. STEINER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSERVATIVE RASTERIZATION OF PRIMITIVES USING AN ERROR TERM
- Publication number 20140267238
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING
- Publication number 20140267232
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIRESOLUTION CONSISTENT RASTERIZATION
- Publication number 20140253555
- Publication date Sep 11, 2014
- NVIDIA Corporation
- Eric B. LUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TILED CACHING
- Publication number 20140118361
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TILED CACHING
- Publication number 20140118364
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE
- Publication number 20140118376
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE HANDLING IN A TILED ARCHITECTURE
- Publication number 20140118380
- Publication date May 1, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY SAMPLE EVALUATION DURING COARSE RASTERIZATION
- Publication number 20130342547
- Publication date Dec 26, 2013
- Eric LUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR REDUCING A POLYGON BOUNDING BOX
- Publication number 20130187956
- Publication date Jul 25, 2013
- Walter R. STEINER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for parallel fine rasterization in a raster stage of a graph...
- Publication number 20070296725
- Publication date Dec 27, 2007
- Walter R. Steiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing a graphics rendering pipeline using early Z-mode
- Publication number 20070257905
- Publication date Nov 8, 2007
- NVIDIA CORPORATION
- Mark J. French
- G06 - COMPUTING CALCULATING COUNTING

Walter R. Steiner

Person

Patents Grantslast 30 patents

State handling in a tiled architecture

Distributed tiled caching

Multiresolution consistent rasterization

Heuristics for improving performance in a tile based architecture

Consistent vertex snapping for variable resolution rendering

Conservative rasterization of primitives using an error term

Method and system for reducing a polygon bounding box

Early sample evaluation during coarse rasterization

Distributed tiled caching

Consistent vertex snapping for variable resolution rendering

Efficient round point rasterization

Optimizing a graphics rendering pipeline using early Z-mode

Method for parallel fine rasterization in a raster stage of a graph...

Method and system for deferred coverage mask generation in a raster...

Patents Applicationslast 30 patents

CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING

EFFICIENT ROUND POINT RASTERIZATION

CONSERVATIVE RASTERIZATION OF PRIMITIVES USING AN ERROR TERM

CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING

MULTIRESOLUTION CONSISTENT RASTERIZATION

DISTRIBUTED TILED CACHING

DISTRIBUTED TILED CACHING

HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE

STATE HANDLING IN A TILED ARCHITECTURE

EARLY SAMPLE EVALUATION DURING COARSE RASTERIZATION

METHOD AND SYSTEM FOR REDUCING A POLYGON BOUNDING BOX

Method for parallel fine rasterization in a raster stage of a graph...

Optimizing a graphics rendering pipeline using early Z-mode