Wang Ling Goh

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with self-aligned line and via
- Patent number 8,766,454
- Issue date Jul 1, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing 3-D spiral stacked inductor on semiconducto...
- Patent number 7,721,414
- Issue date May 25, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Choon-Beng Sia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with self-aligned line and via and manufacturing...
- Patent number 7,119,010
- Issue date Oct 10, 2006
- Chartered Semiconductor Manfacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extended poly buffer STI scheme
- Patent number 7,060,573
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Patent number 6,998,682
- Issue date Feb 14, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Patent number 6,905,919
- Issue date Jun 14, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,849,928
- Issue date Feb 1, 2005
- Chartered Semiconductor Manufacturing, Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3-D spiral stacked inductor on semiconductor material
- Patent number 6,841,847
- Issue date Jan 11, 2005
- Chartered Semiconductor Manufacturing, Ltd.
- Choon-Beng Sia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation using TEOS cap and polysilicon pullback
- Patent number 6,613,648
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Limited
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for buffer STI scheme with a hard mask layer as an oxidation...
- Patent number 6,613,649
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating SOI devices with option of incorporating air...
- Patent number 6,613,652
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,558,994
- Issue date May 6, 2003
- Chartered Semiconductors Maufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,472,697
- Issue date Oct 29, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating complementary silicon on insulator devices u...
- Patent number 6,468,880
- Issue date Oct 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to achieve STI planarization
- Patent number 6,403,484
- Issue date Jun 11, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,399,471
- Issue date Jun 4, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form high performance copper damascene interconnects by d...
- Patent number 6,380,084
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Inc.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to prevent CU dishing during damascene formation
- Patent number 6,376,376
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA
- Publication number 20070075371
- Publication date Apr 5, 2007
- Chartered Semiconductor Manufacturing LTD.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Publication number 20050208712
- Publication date Sep 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing 3-D spiral stacked inductor on semiconducto...
- Publication number 20050057335
- Publication date Mar 17, 2005
- Chartered Semiconductor Manufacturing LTD.
- Choon-Beng Sia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Publication number 20050023608
- Publication date Feb 3, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3-D spiral stacked inductor on semiconductor material
- Publication number 20040041234
- Publication date Mar 4, 2004
- Choon-Beng Sia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with self-aligned line and via and manufacturing...
- Publication number 20030197279
- Publication date Oct 23, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20030107083
- Publication date Jun 12, 2003
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for buffer STI scheme with a hard mask layer as an oxidation...
- Publication number 20030104675
- Publication date Jun 5, 2003
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating SOI devices with option of incorporating air...
- Publication number 20020132448
- Publication date Sep 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assorted aluminum wiring design to enhance chip-level performance f...
- Publication number 20020127834
- Publication date Sep 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20020127816
- Publication date Sep 12, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Extended poly buffer STI scheme
- Publication number 20020094648
- Publication date Jul 18, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS

Wang Ling Goh

Person

Patents Grantslast 30 patents

Integrated circuit with self-aligned line and via

Method of manufacturing 3-D spiral stacked inductor on semiconducto...

Integrated circuit with self-aligned line and via and manufacturing...

Extended poly buffer STI scheme

Method of forming a partially depleted silicon on insulator (PDSOI)...

Method of forming a partially depleted silicon on insulator (PDSOI)...

Dual silicon-on-insulator device wafer die

3-D spiral stacked inductor on semiconductor material

Shallow trench isolation using TEOS cap and polysilicon pullback

Method for buffer STI scheme with a hard mask layer as an oxidation...

Method for fabricating SOI devices with option of incorporating air...

Dual silicon-on-insulator device wafer die

Assorted aluminum wiring design to enhance chip-level performance f...

Method for fabricating complementary silicon on insulator devices u...

Method to achieve STI planarization

Assorted aluminum wiring design to enhance chip-level performance f...

Method to form high performance copper damascene interconnects by d...

Method to prevent CU dishing during damascene formation

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA

Method of forming a partially depleted silicon on insulator (PDSOI)...

Method of manufacturing 3-D spiral stacked inductor on semiconducto...

Method of forming a partially depleted silicon on insulator (PDSOI)...

3-D spiral stacked inductor on semiconductor material

Integrated circuit with self-aligned line and via and manufacturing...

Dual silicon-on-insulator device wafer die

Method for buffer STI scheme with a hard mask layer as an oxidation...

Method for fabricating SOI devices with option of incorporating air...

Assorted aluminum wiring design to enhance chip-level performance f...

Dual silicon-on-insulator device wafer die

Extended poly buffer STI scheme