Warren R. Morrow

Person

Steilacoom, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 12,046,577
- Issue date Jul 23, 2024
- Tahoe Research, LTD.
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 9,768,148
- Issue date Sep 19, 2017
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 8,971,087
- Issue date Mar 3, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,510,612
- Issue date Aug 13, 2013
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,489,944
- Issue date Jul 16, 2013
- Intel Corporation
- Warren Morrow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,286,039
- Issue date Oct 9, 2012
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,135,999
- Issue date Mar 13, 2012
- Intel Corporation
- Warren Morrow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory channel with bit lane fail-over
- Patent number 8,020,056
- Issue date Sep 13, 2011
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory channel with bit lane fail-over
- Patent number 7,761,753
- Issue date Jul 20, 2010
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel with bit lane fail-over
- Patent number 7,386,768
- Issue date Jun 10, 2008
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optical add/drop interconnect bus for multiprocessor architecture
- Patent number 7,366,368
- Issue date Apr 29, 2008
- Intel Corporation
- Warren R. Morrow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for thermal throttling of memory modules
- Patent number 7,318,130
- Issue date Jan 8, 2008
- Intel Corporation
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for memory bandwidth thermal budgetting
- Patent number 7,269,481
- Issue date Sep 11, 2007
- Intel Corporation
- David S. De Lorenzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved mirrored memory systems
- Patent number 7,130,229
- Issue date Oct 31, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers with interleaved mirrored memory modes
- Patent number 7,076,618
- Issue date Jul 11, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers with interleaved mirrored memory modes
- Patent number 7,017,017
- Issue date Mar 21, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing resources in a bus bridge
- Patent number 6,708,240
- Issue date Mar 16, 2004
- Intel Corporation
- Theodore L. Willke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic swing voltage adjustment
- Patent number 6,693,450
- Issue date Feb 17, 2004
- Intel Corporation
- Andrew M. Volk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bus bridging method and apparatus including use of read size indica...
- Patent number 6,502,154
- Issue date Dec 31, 2002
- Intel Corporation
- Susan S. Meredith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to manage digital bus traffic
- Patent number 6,487,627
- Issue date Nov 26, 2002
- Intel Corporation
- Theodore L. Willke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for saving the effective address of floating p...
- Patent number 5,721,857
- Issue date Feb 24, 1998
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rounding operands using previous rounding...
- Patent number 5,612,909
- Issue date Mar 18, 1997
- Intel Corporation
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20240379625
- Publication date Nov 14, 2024
- Tahoe Research, Ltd.
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20190304953
- Publication date Oct 3, 2019
- Intel Corporation
- Pete D. VOGT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
- Publication number 20180122779
- Publication date May 3, 2018
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20150108660
- Publication date Apr 23, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
RELIABILITY ENHANCEMENTS FOR HIGH SPEED MEMORY - PARITY PROTECTION...
- Publication number 20140089755
- Publication date Mar 27, 2014
- Shveta KANTAMSETTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20130272049
- Publication date Oct 17, 2013
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20130097371
- Publication date Apr 18, 2013
- Warren Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20120331356
- Publication date Dec 27, 2012
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20120102256
- Publication date Apr 26, 2012
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20110131370
- Publication date Jun 2, 2011
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHANNEL WITH BIT LANE FAIL-OVER
- Publication number 20100281315
- Publication date Nov 4, 2010
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHANNEL WITH BIT LANE FAIL-OVER
- Publication number 20090013211
- Publication date Jan 8, 2009
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for thermal throttling of memory modules
- Publication number 20050289292
- Publication date Dec 29, 2005
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optical add/drop interconnect bus for multiprocessor architecture
- Publication number 20050276604
- Publication date Dec 15, 2005
- Warren R. Morrow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory controllers with interleaved mirrored memory modes
- Publication number 20050262388
- Publication date Nov 24, 2005
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low latency optical memory bus
- Publication number 20050147414
- Publication date Jul 7, 2005
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for memory bandwidth thermal budgetting
- Publication number 20040267409
- Publication date Dec 30, 2004
- David S. De Lorenzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory channel with bit lane fail-over
- Publication number 20040250181
- Publication date Dec 9, 2004
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleaved mirrored memory systems
- Publication number 20040090827
- Publication date May 13, 2004
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controllers with interleaved mirrored memory modes
- Publication number 20040093472
- Publication date May 13, 2004
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING

Warren R. Morrow

Person

Patents Grantslast 30 patents

Stacked memory with interface providing offset interconnects

Stacked memory with interface providing offset interconnects

Stacked memory with interface providing offset interconnects

Disabling outbound drivers for a last memory buffer on a memory cha...

Disabling outbound drivers for a last memory buffer on a memory cha...

Disabling outbound drivers for a last memory buffer on a memory cha...

Disabling outbound drivers for a last memory buffer on a memory cha...

Memory channel with bit lane fail-over

Memory channel with bit lane fail-over

Memory channel with bit lane fail-over

Optical add/drop interconnect bus for multiprocessor architecture

System and method for thermal throttling of memory modules

Method and apparatus for memory bandwidth thermal budgetting

Interleaved mirrored memory systems

Memory controllers with interleaved mirrored memory modes

Memory controllers with interleaved mirrored memory modes

Managing resources in a bus bridge

Dynamic swing voltage adjustment

Bus bridging method and apparatus including use of read size indica...

Method and apparatus to manage digital bus traffic

Method and apparatus for saving the effective address of floating p...

Method and apparatus for rounding operands using previous rounding...

Patents Applicationslast 30 patents

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

RELIABILITY ENHANCEMENTS FOR HIGH SPEED MEMORY - PARITY PROTECTION...

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

MEMORY CHANNEL WITH BIT LANE FAIL-OVER

MEMORY CHANNEL WITH BIT LANE FAIL-OVER

System and method for thermal throttling of memory modules

Optical add/drop interconnect bus for multiprocessor architecture

Memory controllers with interleaved mirrored memory modes

Low latency optical memory bus

Method and apparatus for memory bandwidth thermal budgetting

Memory channel with bit lane fail-over

Interleaved mirrored memory systems

Memory controllers with interleaved mirrored memory modes