Wayne F. Ellis

Person

Jericho, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-chip package with interconnected stacked chips
- Patent number 8,138,610
- Issue date Mar 20, 2012
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit design
- Patent number 8,099,688
- Issue date Jan 17, 2012
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory refresh system and method
- Patent number 7,975,170
- Issue date Jul 5, 2011
- Qimonda AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure of expanding, upgrading, or fixing multi-chip...
- Patent number 7,944,047
- Issue date May 17, 2011
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for synchronizing memory enabled systems with...
- Patent number 7,882,324
- Issue date Feb 1, 2011
- Qimonda AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing memory enabled systems using...
- Patent number 7,721,010
- Issue date May 18, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-diagnostic scheme for detecting errors
- Patent number 7,694,196
- Issue date Apr 6, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure to share internally generated voltages between chips in MCP
- Patent number 7,688,665
- Issue date Mar 30, 2010
- Qimonda North America Corp.
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated redundancy architecture and method for providing redunda...
- Patent number 7,565,585
- Issue date Jul 21, 2009
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory configured on a common substrate
- Patent number 7,539,034
- Issue date May 26, 2009
- Qimonda North America Corp.
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for performing a command cancel function in a DRAM
- Patent number 7,480,774
- Issue date Jan 20, 2009
- International Business Machines Corporation
- Wayne F. Ellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM voltage control for improved operational margins
- Patent number 7,466,604
- Issue date Dec 16, 2008
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Single exposure of mask levels having a lines and spaces array usin...
- Patent number 7,413,833
- Issue date Aug 19, 2008
- Infineon Technologies AG
- Shahid Butt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carrier for test, burn-in, and first level packaging
- Patent number 7,394,268
- Issue date Jul 1, 2008
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM voltage control for improved operational margins
- Patent number 7,313,032
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance optimizing compiler for building a compiled DRAM
- Patent number 7,305,515
- Issue date Dec 4, 2007
- International Business Machines Corporation
- Louis L. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-cost deep trench decoupling capacitor device and process of man...
- Patent number 7,193,262
- Issue date Mar 20, 2007
- International Business Machines Corporation
- Herbert L. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carrier for test, burn-in, and first level packaging
- Patent number 7,132,841
- Issue date Nov 7, 2006
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
ECC based system and method for repairing failed memory elements
- Patent number 7,085,971
- Issue date Aug 1, 2006
- International Business Machines Corporation
- John E. Barth, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic timing analyzer
- Patent number 6,912,665
- Issue date Jun 28, 2005
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous dynamic random access memory device having memory comma...
- Patent number 6,826,113
- Issue date Nov 30, 2004
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable DC voltage generator system
- Patent number 6,737,907
- Issue date May 18, 2004
- International Business Machines Corporation
- Louis L. Hsu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
System and method for measuring circuit performance degradation due...
- Patent number 6,731,179
- Issue date May 4, 2004
- International Business Machines Corporation
- Wagdi William Abadeer
- G01 - MEASURING TESTING
Information Patent Grant
Asymmetric gates for high density DRAM
- Patent number 6,670,667
- Issue date Dec 30, 2003
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Word line driver for dynamic random access memories
- Patent number 6,646,949
- Issue date Nov 11, 2003
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM word line voltage control to insure full cell writeback level
- Patent number 6,580,650
- Issue date Jun 17, 2003
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing circuit and method for a compilable DRAM
- Patent number 6,538,932
- Issue date Mar 25, 2003
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power DC voltage generator system
- Patent number 6,507,237
- Issue date Jan 14, 2003
- IBM Corporation
- Louis L. Hsu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Asymmetric gates for high density DRAM
- Patent number 6,458,646
- Issue date Oct 1, 2002
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM array interchangeable between single-cell and twin-cell array...
- Patent number 6,452,855
- Issue date Sep 17, 2002
- International Business Machines Corp.
- Louis L. Hsu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE
- Publication number 20090200652
- Publication date Aug 13, 2009
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS
- Publication number 20090129186
- Publication date May 21, 2009
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Structure for SRAM voltage control for improved operational margins
- Publication number 20090129191
- Publication date May 21, 2009
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...
- Publication number 20090113158
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...
- Publication number 20090113078
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...
- Publication number 20090079055
- Publication date Mar 26, 2009
- JONG HOON OH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
- Publication number 20090080279
- Publication date Mar 26, 2009
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY REFRESH SYSTEM AND METHOD
- Publication number 20080313494
- Publication date Dec 18, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configured on a common substrate
- Publication number 20080189480
- Publication date Aug 7, 2008
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM voltage control for improved operational margins
- Publication number 20080089116
- Publication date Apr 17, 2008
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
- Publication number 20070121370
- Publication date May 31, 2007
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
CARRIER FOR TEST, BURN-IN, AND FIRST LEVEL PACKAGING
- Publication number 20070001708
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Claude L. Bertin
- G01 - MEASURING TESTING
Information Patent Application
Low-Cost Deep Trench Decoupling Capacitor Device and Process of Man...
- Publication number 20060124982
- Publication date Jun 15, 2006
- International Business Machines Corporation
- Herbert L. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Single exposure of mask levels having a lines and spaces array usin...
- Publication number 20050255387
- Publication date Nov 17, 2005
- Infineon Technologies North America Corp.
- Shahid Butt
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Integrated Redundancy Architecture and Method for Providing Redunda...
- Publication number 20050160310
- Publication date Jul 21, 2005
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
GATE LENGTH PROXIMITY CORRECTED DEVICE
- Publication number 20050009312
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Shahid Butt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PERFORMING A COMMAND CANCEL FUNCTION IN A DRAM
- Publication number 20040199715
- Publication date Oct 7, 2004
- International Business Machines Corporation
- Wayne F. Ellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE HAVING MEMORY COMMA...
- Publication number 20040190365
- Publication date Sep 30, 2004
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for measuring circuit performance degradation due...
- Publication number 20030189465
- Publication date Oct 9, 2003
- International Business Machines Corporation
- Wagdi William Abadeer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ECC Based system and method for repairing failed memory elements
- Publication number 20030084386
- Publication date May 1, 2003
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable DC voltage generator system
- Publication number 20030052729
- Publication date Mar 20, 2003
- International Business Machines Corporation
- Louis L. Hsu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Timing circuit and method for a compilable dram
- Publication number 20020191448
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetric gates for high density DRAM
- Publication number 20020192912
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Automatic timing analyzer
- Publication number 20020194539
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Wayne F. Ellis
- G01 - MEASURING TESTING
Information Patent Application
Performance optimizing compiler for building a compiled DRAM
- Publication number 20020170019
- Publication date Nov 14, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM word line voltage control to insure full cell writeback level
- Publication number 20020159301
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
Dram array interchangeable between single-cell and twin-cell array...
- Publication number 20020089872
- Publication date Jul 11, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
Low-power DC voltage generator system
- Publication number 20020057126
- Publication date May 16, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G05 - CONTROLLING REGULATING
Information Patent Application
Structures for wafer level test and burn -in
- Publication number 20010046168
- Publication date Nov 29, 2001
- John E. Barth
- G01 - MEASURING TESTING
Information Patent Application
Rolling ball connector
- Publication number 20010002330
- Publication date May 31, 2001
- Joseph A. Benenati
- G01 - MEASURING TESTING

Wayne F. Ellis

Person

Patents Grantslast 30 patents

Multi-chip package with interconnected stacked chips

Circuit design

Memory refresh system and method

Method and structure of expanding, upgrading, or fixing multi-chip...

Method and apparatus for synchronizing memory enabled systems with...

Method and apparatus for implementing memory enabled systems using...

Self-diagnostic scheme for detecting errors

Structure to share internally generated voltages between chips in MCP

Integrated redundancy architecture and method for providing redunda...

Memory configured on a common substrate

Method for performing a command cancel function in a DRAM

SRAM voltage control for improved operational margins

Single exposure of mask levels having a lines and spaces array usin...

Carrier for test, burn-in, and first level packaging

SRAM voltage control for improved operational margins

Performance optimizing compiler for building a compiled DRAM

Low-cost deep trench decoupling capacitor device and process of man...

Carrier for test, burn-in, and first level packaging

ECC based system and method for repairing failed memory elements

Automatic timing analyzer

Synchronous dynamic random access memory device having memory comma...

Programmable DC voltage generator system

System and method for measuring circuit performance degradation due...

Asymmetric gates for high density DRAM

Word line driver for dynamic random access memories

DRAM word line voltage control to insure full cell writeback level

Timing circuit and method for a compilable DRAM

Low-power DC voltage generator system

Asymmetric gates for high density DRAM

DRAM array interchangeable between single-cell and twin-cell array...

Patents Applicationslast 30 patents

METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE

SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS

Structure for SRAM voltage control for improved operational margins

METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...

METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...

METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...

STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP

MEMORY REFRESH SYSTEM AND METHOD

Memory configured on a common substrate

SRAM voltage control for improved operational margins

SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS

CARRIER FOR TEST, BURN-IN, AND FIRST LEVEL PACKAGING

Low-Cost Deep Trench Decoupling Capacitor Device and Process of Man...

Single exposure of mask levels having a lines and spaces array usin...

Integrated Redundancy Architecture and Method for Providing Redunda...

GATE LENGTH PROXIMITY CORRECTED DEVICE

METHOD FOR PERFORMING A COMMAND CANCEL FUNCTION IN A DRAM

SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE HAVING MEMORY COMMA...

System and method for measuring circuit performance degradation due...

ECC Based system and method for repairing failed memory elements

Programmable DC voltage generator system

Timing circuit and method for a compilable dram

Asymmetric gates for high density DRAM

Automatic timing analyzer

Performance optimizing compiler for building a compiled DRAM

DRAM word line voltage control to insure full cell writeback level

Dram array interchangeable between single-cell and twin-cell array...

Low-power DC voltage generator system

Structures for wafer level test and burn -in

Rolling ball connector