Wei Hwang

Person

Salamanca La Verna, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aware adaptive power control system and a method for determini...
- Patent number 8,138,795
- Issue date Mar 20, 2012
- National Chiao Tung University
- Wei-Chih Hseih
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Butterfly match-line structure and search method implemented thereby
- Patent number 7,903,443
- Issue date Mar 8, 2011
- National Chiao Tung University
- Po-Tsang Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage current cut-off device for ternary content addressable memory
- Patent number 7,738,275
- Issue date Jun 15, 2010
- National Chiao Tung University
- Po-Tsang Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Super leakage current cut-off device for ternary content addressabl...
- Patent number 7,616,469
- Issue date Nov 10, 2009
- National Chiao Tung University
- Po-Tsang Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Stored don't-care based hierarchical search-line scheme
- Patent number 7,525,827
- Issue date Apr 28, 2009
- National Chiao Tung University
- Shu-Wei Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
XOR-based conditional keeper and an architecture implementing its a...
- Patent number 7,358,768
- Issue date Apr 15, 2008
- National Chiao Tung University
- Chung-Hsien Hua
- G11 - INFORMATION STORAGE
Information Patent Grant
Comparator eliminating need for one's complement logic for signed n...
- Patent number 7,284,028
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Wei Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock switching circuit
- Patent number 7,259,598
- Issue date Aug 21, 2007
- National Chiao Tung University
- Jian-Hua Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous first-in-first-out cell
- Patent number 7,260,008
- Issue date Aug 21, 2007
- National Chiao Tung University
- Yeh-Lin Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gating structure having data retention and intermediate modes
- Patent number 7,190,187
- Issue date Mar 13, 2007
- National Chiao Tung University
- Chung-Hsien Hua
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-type thin-film field-effect transistors and applications
- Patent number 6,890,766
- Issue date May 10, 2005
- International Business Machines Corporation
- Thomas Doderer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merged logic and memory combining thin film and bulk Si transistors
- Patent number 6,620,659
- Issue date Sep 16, 2003
- International Business Machines Corporation
- Philip George Emmma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating flash memory device using dual damascene pro...
- Patent number 6,492,227
- Issue date Dec 10, 2002
- International Business Machines Corporation
- Li-Kong Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data retention registers
- Patent number 6,437,623
- Issue date Aug 20, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G01 - MEASURING TESTING
Information Patent Grant
High performance semiconductor memory device with low power consump...
- Patent number 6,307,805
- Issue date Oct 23, 2001
- International Business Machines Corporation
- John E. Andersen
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoupling capacitor structure distributed above an integrated circ...
- Patent number 6,285,050
- Issue date Sep 4, 2001
- International Business Machines Corporation
- Philip George Emma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Provably correct storage arrays
- Patent number 6,279,144
- Issue date Aug 21, 2001
- International Business Machines Corporation
- Walter Harvey Henkels
- G01 - MEASURING TESTING
Information Patent Grant
Merged logic and memory combining thin film and bulk Si transistors
- Patent number 6,271,542
- Issue date Aug 7, 2001
- International Business Machines Corporation
- Philip George Emma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of self programmed built in self test
- Patent number 6,230,290
- Issue date May 8, 2001
- International Business Machines Corporation
- David F. Heidel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for tuning of components for integrated circuits
- Patent number 6,219,822
- Issue date Apr 17, 2001
- International Business Machines Corporation
- George D. Gristede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for selecting sizes of components for integrated...
- Patent number 6,175,949
- Issue date Jan 16, 2001
- International Business Machines Corporation
- George D. Gristede
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous multiport register file with self resetting write oper...
- Patent number 6,151,266
- Issue date Nov 21, 2000
- International Business Machines Corporation
- Walter Harvey Henkels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self programmed built in self test
- Patent number 6,108,798
- Issue date Aug 22, 2000
- International Business Machines Corporation
- David F. Heidel
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-threshold-voltage differential cascode voltage switch (DCVS)...
- Patent number 6,090,153
- Issue date Jul 18, 2000
- International Business Machines Corporation
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design of provably correct storage arrays
- Patent number 5,995,425
- Issue date Nov 30, 1999
- International Business Machines Corporation
- Walter Harvey Henkels
- G01 - MEASURING TESTING
Information Patent Grant
Pulse-to-static conversion latch with a self-timed control circuit
- Patent number 5,973,529
- Issue date Oct 26, 1999
- International Business Machines Corporation
- Terry Ivan Chappell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input isolation for self-resetting CMOS macros
- Patent number 5,939,898
- Issue date Aug 17, 1999
- International Business Machines Corporation
- Walter Harvey Henkels
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Emulating quasi-synchronous DRAM with asynchronous DRAM
- Patent number 5,901,304
- Issue date May 4, 1999
- International Business Machines Corporation
- Wei Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip layout compilation
- Patent number 5,883,814
- Issue date Mar 16, 1999
- International Business Machines Corporation
- Wing K. Luk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
X+2X adder with multi-bit generate/propagate circuit
- Patent number 5,875,125
- Issue date Feb 23, 1999
- International Business Machines Corporation
- Wei Hwang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Super leakage current cut-off device for ternary content addressabl...
- Publication number 20090161399
- Publication date Jun 25, 2009
- Po-Tsang Huang
- G11 - INFORMATION STORAGE
Information Patent Application
BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY
- Publication number 20080177944
- Publication date Jul 24, 2008
- Po-Tsang Huang
- G11 - INFORMATION STORAGE
Information Patent Application
STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME
- Publication number 20080175030
- Publication date Jul 24, 2008
- Shu-Wei CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
Pipeline-based reconfigurable mixed-radix FFT processor
- Publication number 20080155003
- Publication date Jun 26, 2008
- National Chiao Tung University
- Chi-Chen Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock switching circuit
- Publication number 20070152719
- Publication date Jul 5, 2007
- Jian-Hua Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
XOR-based conditional keeper and an architecture implementing its a...
- Publication number 20070103885
- Publication date May 10, 2007
- Chung-Hsien Hua
- G11 - INFORMATION STORAGE
Information Patent Application
Asynchronous first-in first-out cell
- Publication number 20070097771
- Publication date May 3, 2007
- Yeh-Lin Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power gating structure having data retention and intermediate modes
- Publication number 20060119393
- Publication date Jun 8, 2006
- National Chiao Tung University
- Chung-Hsien Hua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable voltage generator
- Publication number 20050174162
- Publication date Aug 11, 2005
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Tung-Shuan Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
Comparator eliminating need for one's complement logic for signed n...
- Publication number 20040088591
- Publication date May 6, 2004
- International Business Machines Corporation
- Wei Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual-type thin-film field-effect transistors and applications
- Publication number 20030201495
- Publication date Oct 30, 2003
- Thomas Doderer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Merged logic and memory combining thin film and bulk Si transistors
- Publication number 20010028059
- Publication date Oct 11, 2001
- Philip George Emma
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Self-aware adaptive power control system and a method for determini...

Butterfly match-line structure and search method implemented thereby

Leakage current cut-off device for ternary content addressable memory

Super leakage current cut-off device for ternary content addressabl...

Stored don't-care based hierarchical search-line scheme

XOR-based conditional keeper and an architecture implementing its a...

Comparator eliminating need for one's complement logic for signed n...

Clock switching circuit

Asynchronous first-in-first-out cell

Power gating structure having data retention and intermediate modes

Dual-type thin-film field-effect transistors and applications

Merged logic and memory combining thin film and bulk Si transistors

Method for fabricating flash memory device using dual damascene pro...

Data retention registers

High performance semiconductor memory device with low power consump...

Decoupling capacitor structure distributed above an integrated circ...

Provably correct storage arrays

Merged logic and memory combining thin film and bulk Si transistors

Method of self programmed built in self test

Method and system for tuning of components for integrated circuits

Method and system for selecting sizes of components for integrated...

Asynchronous multiport register file with self resetting write oper...

Self programmed built in self test

Multi-threshold-voltage differential cascode voltage switch (DCVS)...

Design of provably correct storage arrays

Pulse-to-static conversion latch with a self-timed control circuit

Input isolation for self-resetting CMOS macros

Emulating quasi-synchronous DRAM with asynchronous DRAM

System-on-chip layout compilation

X+2X adder with multi-bit generate/propagate circuit

Patents Applicationslast 30 patents

Super leakage current cut-off device for ternary content addressabl...

BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY

STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME

Pipeline-based reconfigurable mixed-radix FFT processor

Clock switching circuit

XOR-based conditional keeper and an architecture implementing its a...

Asynchronous first-in first-out cell

Power gating structure having data retention and intermediate modes

Configurable voltage generator

Comparator eliminating need for one's complement logic for signed n...

Dual-type thin-film field-effect transistors and applications

Merged logic and memory combining thin film and bulk Si transistors