Wei-Jen Hsia

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 7,393,780
- Issue date Jul 1, 2008
- LSI Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,312,127
- Issue date Dec 25, 2007
- LSI Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect dielectric tuning
- Patent number 7,259,462
- Issue date Aug 21, 2007
- LSI Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarization with reduced dishing
- Patent number 7,220,362
- Issue date May 22, 2007
- LSI Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect dielectric tuning
- Patent number 7,081,406
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 7,071,094
- Issue date Jul 4, 2006
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,064,062
- Issue date Jun 20, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarization with reduced dishing
- Patent number 7,029,591
- Issue date Apr 18, 2006
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Plasma treatment of low dielectric constant dielectric material to...
- Patent number 6,930,056
- Issue date Aug 16, 2005
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarizing upper surface of damascene wiring structure...
- Patent number 6,881,664
- Issue date Apr 19, 2005
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 6,812,134
- Issue date Nov 2, 2004
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure having low dielectric constant materia...
- Patent number 6,794,756
- Issue date Sep 21, 2004
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment of low dielectric constant dielectric material to...
- Patent number 6,790,784
- Issue date Sep 14, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for forming dielectric layers having reduced d...
- Patent number 6,774,057
- Issue date Aug 10, 2004
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant silicon oxide-based dielectric layer for in...
- Patent number 6,756,674
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Anti-reflective coatings for use at 248 nm and 193 nm
- Patent number 6,686,272
- Issue date Feb 3, 2004
- LSI Logic Corporation
- Sang-Yun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming integrated circuit structure comprising layer o...
- Patent number 6,613,665
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for treating porous low k dielectric material in damascene...
- Patent number 6,537,896
- Issue date Mar 25, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATER...
- Patent number 6,528,423
- Issue date Mar 4, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming metal-filled openings in low dielectric constan...
- Patent number 6,503,840
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite low dielectric constant film for integrated circuit struc...
- Patent number 6,492,731
- Issue date Dec 10, 2002
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming integrated circuit structure having low dielectri...
- Patent number 6,423,628
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming low K dielectric material between metal lines
- Patent number 6,423,630
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for inhibiting crack formation in low dielectric constant d...
- Patent number 6,420,277
- Issue date Jul 16, 2002
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for treating damaged surfaces of low k carbon doped silicon...
- Patent number 6,346,490
- Issue date Feb 12, 2002
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to obtain a low resistivity and conformity chemical vapor de...
- Patent number 6,297,555
- Issue date Oct 2, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to prevent stress cracking of dielectric films on semicondu...
- Patent number 6,232,658
- Issue date May 15, 2001
- LSI Logic Corporation
- Wilbur G. Catabay
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Plasma cleaning process for openings formed in at least one low die...
- Patent number 6,204,192
- Issue date Mar 20, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and composition for reducing gate oxide damage during RF spu...
- Patent number 6,204,550
- Issue date Mar 20, 2001
- LSI Logic Corporation
- Zhihai Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming low k silicon oxide dielectric material while s...
- Patent number 6,147,012
- Issue date Nov 14, 2000
- LSI Logic Corporation
- Valeriy Sukharev
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATI...
- Publication number 20080308937
- Publication date Dec 18, 2008
- SVTC TECHNOLOGIES, LLC
- Wilbur Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planarization with reduced dishing
- Publication number 20070163993
- Publication date Jul 19, 2007
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Dual layer barrier film techniques to prevent resist poisoning
- Publication number 20060205203
- Publication date Sep 14, 2006
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20060166496
- Publication date Jul 27, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planarization with reduced dishing
- Publication number 20060118523
- Publication date Jun 8, 2006
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interconnection capacitance reduction
- Publication number 20060035457
- Publication date Feb 16, 2006
- Richard J. Carter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect dielectric tuning
- Publication number 20060035455
- Publication date Feb 16, 2006
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20050127458
- Publication date Jun 16, 2005
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual layer barrier film techniques to prevent resist poisoning
- Publication number 20040253784
- Publication date Dec 16, 2004
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planarization with reduced dishing
- Publication number 20040238492
- Publication date Dec 2, 2004
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Process for planarizing upper surface of damascene wiring structure...
- Publication number 20040009668
- Publication date Jan 15, 2004
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Plasma treatment of low dielectric constant dielectric material to...
- Publication number 20030207594
- Publication date Nov 6, 2003
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for forming metal-filled openings in low dielectric constan...
- Publication number 20020164877
- Publication date Nov 7, 2002
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit structure having low dielectric constant materia...
- Publication number 20020135040
- Publication date Sep 26, 2002
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS

Wei-Jen Hsia

Person

Patents Grantslast 30 patents

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Interconnect dielectric tuning

Planarization with reduced dishing

Interconnect dielectric tuning

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Planarization with reduced dishing

Plasma treatment of low dielectric constant dielectric material to...

Process for planarizing upper surface of damascene wiring structure...

Dual layer barrier film techniques to prevent resist poisoning

Integrated circuit structure having low dielectric constant materia...

Plasma treatment of low dielectric constant dielectric material to...

Method and structure for forming dielectric layers having reduced d...

Low dielectric constant silicon oxide-based dielectric layer for in...

Anti-reflective coatings for use at 248 nm and 193 nm

Process for forming integrated circuit structure comprising layer o...

Process for treating porous low k dielectric material in damascene...

PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATER...

Process for forming metal-filled openings in low dielectric constan...

Composite low dielectric constant film for integrated circuit struc...

Method of forming integrated circuit structure having low dielectri...

Process for forming low K dielectric material between metal lines

Process for inhibiting crack formation in low dielectric constant d...

Process for treating damaged surfaces of low k carbon doped silicon...

Method to obtain a low resistivity and conformity chemical vapor de...

Process to prevent stress cracking of dielectric films on semicondu...

Plasma cleaning process for openings formed in at least one low die...

Method and composition for reducing gate oxide damage during RF spu...

Process for forming low k silicon oxide dielectric material while s...

Patents Applicationslast 30 patents

COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATI...

Planarization with reduced dishing

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Planarization with reduced dishing

Interconnection capacitance reduction

Interconnect dielectric tuning

Incorporating dopants to enhance the dielectric properties of metal...

Dual layer barrier film techniques to prevent resist poisoning

Planarization with reduced dishing

Process for planarizing upper surface of damascene wiring structure...

Plasma treatment of low dielectric constant dielectric material to...

Process for forming metal-filled openings in low dielectric constan...

Integrated circuit structure having low dielectric constant materia...