Wei-Jin Dai

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for implementing electronic design entry
- Patent number 8,095,898
- Issue date Jan 10, 2012
- Cadence Design Systems, Inc.
- Ping-Chih Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC layout system having separate trial and detailed routing phases
- Patent number 6,782,520
- Issue date Aug 24, 2004
- Cadence Design Systems, Inc.
- Mitsuru Igusa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis for mixed domain clocks
- Patent number 6,782,519
- Issue date Aug 24, 2004
- Cadence Design Systems, Inc.
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis for a hierarchically partitioned IC layout
- Patent number 6,751,786
- Issue date Jun 15, 2004
- Cadence Design Systems, Inc.
- Chin-Chi Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable, partitioning integrated circuit layout system
- Patent number 6,651,235
- Issue date Nov 18, 2003
- Cadence Design Systems, Inc.
- Wei-Jin Dai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a partitioned IC layout
- Patent number 6,578,183
- Issue date Jun 10, 2003
- Silicon Perspective Corporation
- Kit-Lam Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit partitioning placement and routing system
- Patent number 6,519,749
- Issue date Feb 11, 2003
- Silicon Perspective Corporation
- Ping Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design hierarchy-based placement
- Patent number 6,249,902
- Issue date Jun 19, 2001
- Silicon Perspective Corporation
- Mitsuru Igusa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch optimization in hardware logic emulation systems
- Patent number 5,886,904
- Issue date Mar 23, 1999
- Quickturn Design Systems, Inc.
- Wei-Jin Dai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of removing gated clocks from the clock nets of a netlist fo...
- Patent number 5,452,239
- Issue date Sep 19, 1995
- Quickturn Design Systems, Inc.
- Wei-Jin Dai
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Clock tree synthesis for a hierarchically partitioned IC layout
- Publication number 20030208736
- Publication date Nov 6, 2003
- Chin-Chi Teng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock tree synthesis for mixed domain clocks
- Publication number 20030182634
- Publication date Sep 25, 2003
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gated clock tree synthesis
- Publication number 20030135836
- Publication date Jul 17, 2003
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable, partitioning integrated circuit layout system
- Publication number 20030084416
- Publication date May 1, 2003
- Wei-Jin Dai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING A PARTITIONED IC LAYOUT
- Publication number 20030079192
- Publication date Apr 24, 2003
- Kit-Lam Cheong
- G06 - COMPUTING CALCULATING COUNTING

Wei-Jin Dai

Person

Patents Grantslast 30 patents

Method and system for implementing electronic design entry

IC layout system having separate trial and detailed routing phases

Clock tree synthesis for mixed domain clocks

Clock tree synthesis for a hierarchically partitioned IC layout

Scalable, partitioning integrated circuit layout system

Method for generating a partitioned IC layout

Integrated circuit partitioning placement and routing system

Design hierarchy-based placement

Latch optimization in hardware logic emulation systems

Method of removing gated clocks from the clock nets of a netlist fo...

Patents Applicationslast 30 patents

Clock tree synthesis for a hierarchically partitioned IC layout

Clock tree synthesis for mixed domain clocks

Gated clock tree synthesis

Scalable, partitioning integrated circuit layout system

METHOD FOR GENERATING A PARTITIONED IC LAYOUT