WEI-LIEN YANG

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data interface sleep mode logic
- Patent number 9,280,509
- Issue date Mar 8, 2016
- Intel Corporation
- Wei-Lien Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power oversampling with reduced-architecture delay locked loop
- Patent number 9,231,753
- Issue date Jan 5, 2016
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interface synchronization
- Patent number 9,160,585
- Issue date Oct 13, 2015
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power oversampling with delay locked loop implementation
- Patent number 9,143,314
- Issue date Sep 22, 2015
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power transmitter for generating pulse modulated signals
- Patent number 9,130,817
- Issue date Sep 8, 2015
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interface clock generation
- Patent number 8,890,726
- Issue date Nov 18, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pulse width modulation receiver circuitry
- Patent number 8,848,850
- Issue date Sep 30, 2014
- Intel Corporation
- Wei-Lien Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power data recovery
- Patent number 8,823,432
- Issue date Sep 2, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interface alignment
- Patent number 8,816,885
- Issue date Aug 26, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power oversampling with reduced-architecture delay locked loop
- Patent number 8,797,075
- Issue date Aug 5, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power oversampling with delay locked loop implementation
- Patent number 8,779,815
- Issue date Jul 15, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interface clock generation
- Patent number 8,692,699
- Issue date Apr 8, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power data recovery
- Patent number 8,653,868
- Issue date Feb 18, 2014
- Intel Corporation
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
TECHNOLOGIES FOR MANAGING DISAGGREGATED RESOURCES IN A DATA CENTER
- Publication number 20200257566
- Publication date Aug 13, 2020
- Intel Corporation
- Mrittika GANGULI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Power Oversampling With Reduced-Architecture Delay Locked Loop
- Publication number 20140369400
- Publication date Dec 18, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Low Power Oversampling With Delay Locked Loop Implementation
- Publication number 20140294060
- Publication date Oct 2, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW POWER TRANSMITTER FOR GENERATING PULSE MODULATED SIGNALS
- Publication number 20140226708
- Publication date Aug 14, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA INTERFACE SYNCHRONIZATION
- Publication number 20140211894
- Publication date Jul 31, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA INTERFACE CLOCK GENERATION
- Publication number 20140159780
- Publication date Jun 12, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW POWER DATA RECOVERY
- Publication number 20140103978
- Publication date Apr 17, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PULSE WIDTH MODULATION RECEIVER CIRCUITRY
- Publication number 20140086363
- Publication date Mar 27, 2014
- Intel Corporation
- Wei-Lien Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA INTERFACE CLOCK GENERATION
- Publication number 20140015581
- Publication date Jan 16, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA INTERFACE ALIGNMENT
- Publication number 20140002283
- Publication date Jan 2, 2014
- WEI-LIEN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INTERFACE SLEEP MODE LOGIC
- Publication number 20140006840
- Publication date Jan 2, 2014
- WEI-LIEN YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER DATA RECOVERY
- Publication number 20140002153
- Publication date Jan 2, 2014
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Low Power Oversampling With Reduced-Architecture Delay Locked Loop
- Publication number 20130342249
- Publication date Dec 26, 2013
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Low Power Oversampling With Delay Locked Loop Implementation
- Publication number 20130342248
- Publication date Dec 26, 2013
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW POWER DATA RECOVERY USING OVER-CLOCKING
- Publication number 20130272368
- Publication date Oct 17, 2013
- Wei-Lien Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

WEI-LIEN YANG

Person

Patents Grantslast 30 patents

Data interface sleep mode logic

Low power oversampling with reduced-architecture delay locked loop

Data interface synchronization

Low power oversampling with delay locked loop implementation

Low power transmitter for generating pulse modulated signals

Data interface clock generation

Pulse width modulation receiver circuitry

Low power data recovery

Data interface alignment

Low power oversampling with reduced-architecture delay locked loop

Low power oversampling with delay locked loop implementation

Data interface clock generation

Low power data recovery

Patents Applicationslast 30 patents

TECHNOLOGIES FOR MANAGING DISAGGREGATED RESOURCES IN A DATA CENTER

Low Power Oversampling With Reduced-Architecture Delay Locked Loop

Low Power Oversampling With Delay Locked Loop Implementation

LOW POWER TRANSMITTER FOR GENERATING PULSE MODULATED SIGNALS

DATA INTERFACE SYNCHRONIZATION

DATA INTERFACE CLOCK GENERATION

LOW POWER DATA RECOVERY

PULSE WIDTH MODULATION RECEIVER CIRCUITRY

DATA INTERFACE CLOCK GENERATION

DATA INTERFACE ALIGNMENT

DATA INTERFACE SLEEP MODE LOGIC

LOW POWER DATA RECOVERY

Low Power Oversampling With Reduced-Architecture Delay Locked Loop

Low Power Oversampling With Delay Locked Loop Implementation

LOW POWER DATA RECOVERY USING OVER-CLOCKING