Wilbur C. Catabay

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dielectric barrier layer for increasing electromigration lifetimes...
- Patent number 8,043,968
- Issue date Oct 25, 2011
- LSI Logic Corporation
- Hao Cui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Patent number 7,956,401
- Issue date Jun 7, 2011
- LSI Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Dielectric barrier layer for increasing electromigration lifetimes...
- Patent number 7,728,433
- Issue date Jun 1, 2010
- LSI Corporation
- Hao Cui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming copper interconnects with Sn coatings
- Patent number 7,675,177
- Issue date Mar 9, 2010
- LSI Corporation
- Hongqiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structure for forming copper barrier layers integral wi...
- Patent number 7,646,077
- Issue date Jan 12, 2010
- LSI Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Patent number 7,619,272
- Issue date Nov 17, 2009
- LSI Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Dielectric barrier films for use as copper barrier layers in semico...
- Patent number 7,427,563
- Issue date Sep 23, 2008
- LSI Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-step process for forming a barrier film for use in copper lay...
- Patent number 7,413,984
- Issue date Aug 19, 2008
- LSI Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 7,393,780
- Issue date Jul 1, 2008
- LSI Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,312,127
- Issue date Dec 25, 2007
- LSI Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electro chemical mechanical polishing method and device for planari...
- Patent number 7,285,145
- Issue date Oct 23, 2007
- LSI Corporation
- Mei Zhu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dielectric barrier layer for increasing electromigration lifetimes...
- Patent number 7,276,441
- Issue date Oct 2, 2007
- LSI Logic Corporation
- Hao Cui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect dielectric tuning
- Patent number 7,259,462
- Issue date Aug 21, 2007
- LSI Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-step process for forming a barrier film for use in copper lay...
- Patent number 7,229,923
- Issue date Jun 12, 2007
- LSI Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarization with reduced dishing
- Patent number 7,220,362
- Issue date May 22, 2007
- LSI Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect dielectric tuning
- Patent number 7,081,406
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 7,071,094
- Issue date Jul 4, 2006
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,064,062
- Issue date Jun 20, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarization with reduced dishing
- Patent number 7,029,591
- Issue date Apr 18, 2006
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dielectric barrier films for use as copper barrier layers in semico...
- Patent number 6,939,800
- Issue date Sep 6, 2005
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Viscous electropolishing system
- Patent number 6,935,933
- Issue date Aug 30, 2005
- LSI Logic Corporation
- Valeriy Sukharev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment of low dielectric constant dielectric material to...
- Patent number 6,930,056
- Issue date Aug 16, 2005
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra low dielectric constant thin film
- Patent number 6,905,909
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Hao Cui
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Forming copper interconnects with Sn coatings
- Patent number 6,884,720
- Issue date Apr 26, 2005
- LSI Logic Corporation
- Hongqiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarizing upper surface of damascene wiring structure...
- Patent number 6,881,664
- Issue date Apr 19, 2005
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via and metal line interface capable of reducing the incidence of e...
- Patent number 6,875,693
- Issue date Apr 5, 2005
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electro chemical mechanical polishing method
- Patent number 6,858,531
- Issue date Feb 22, 2005
- LSI Logic Corporation
- Mei Zhu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dual layer barrier film techniques to prevent resist poisoning
- Patent number 6,812,134
- Issue date Nov 2, 2004
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low k dielectric composite layer for integrated circuit structure w...
- Patent number 6,800,940
- Issue date Oct 5, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure having low dielectric constant materia...
- Patent number 6,794,756
- Issue date Sep 21, 2004
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES...
- Publication number 20100200993
- Publication date Aug 12, 2010
- LSI Corporation
- Hao Cui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CUR...
- Publication number 20100022060
- Publication date Jan 28, 2010
- LSI Corporation
- Wai LO
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
CARBON NANOTUBE MEMORY CELLS HAVING FLAT BOTTOM ELECTRODE CONTACT S...
- Publication number 20090256217
- Publication date Oct 15, 2009
- LSI Logic Corporation
- Hongquiang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATI...
- Publication number 20080308937
- Publication date Dec 18, 2008
- SVTC TECHNOLOGIES, LLC
- Wilbur Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICO...
- Publication number 20080303155
- Publication date Dec 11, 2008
- LSI Corporation
- Hong-Qiang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES...
- Publication number 20070190784
- Publication date Aug 16, 2007
- LSI CORPORATION
- Hao Cui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAY...
- Publication number 20070178692
- Publication date Aug 2, 2007
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planarization with reduced dishing
- Publication number 20070163993
- Publication date Jul 19, 2007
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Carbon nanotube memory cells having flat bottom electrode contact s...
- Publication number 20060237799
- Publication date Oct 26, 2006
- LSI Logic Corporation
- Hongquiang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
Dual layer barrier film techniques to prevent resist poisoning
- Publication number 20060205203
- Publication date Sep 14, 2006
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20060166496
- Publication date Jul 27, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Publication number 20060118919
- Publication date Jun 8, 2006
- LSI Logic Corporation, a Delaware Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Planarization with reduced dishing
- Publication number 20060118523
- Publication date Jun 8, 2006
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interconnection capacitance reduction
- Publication number 20060035457
- Publication date Feb 16, 2006
- Richard J. Carter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect dielectric tuning
- Publication number 20060035455
- Publication date Feb 16, 2006
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improved local planarity control during electropolishing
- Publication number 20050224358
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Dielectric barrier films for use as copper barrier layers in semico...
- Publication number 20050208758
- Publication date Sep 22, 2005
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra low dielectric constant thin film
- Publication number 20050176216
- Publication date Aug 11, 2005
- LSI Logic Corporation, Inc.
- Hao Cui
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20050127458
- Publication date Jun 16, 2005
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA LOW DIELECTRIC CONSTANT THIN FILM
- Publication number 20050090036
- Publication date Apr 28, 2005
- Hao Cui
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Via and metal line interface capable of reducing the incidence of e...
- Publication number 20050064708
- Publication date Mar 24, 2005
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual layer barrier film techniques to prevent resist poisoning
- Publication number 20040253784
- Publication date Dec 16, 2004
- LSI Logic Corporation
- Hong-Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planarization with reduced dishing
- Publication number 20040238492
- Publication date Dec 2, 2004
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interconnect integration
- Publication number 20040238960
- Publication date Dec 2, 2004
- LSI Logic Corporation
- Valeriy Sukharev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-step process for forming a barrier film for use in copper lay...
- Publication number 20040157425
- Publication date Aug 12, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for planarizing upper surface of damascene wiring structure...
- Publication number 20040009668
- Publication date Jan 15, 2004
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Plasma treatment of low dielectric constant dielectric material to...
- Publication number 20030207594
- Publication date Nov 6, 2003
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrate processing system
- Publication number 20030084587
- Publication date May 8, 2003
- LSI Logic Corporation
- Kiran Kumar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Diamond barrier layer
- Publication number 20030064588
- Publication date Apr 3, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier and seed layer system
- Publication number 20030064593
- Publication date Apr 3, 2003
- LSI Logic Corporation
- Kiran Kumar
- H01 - BASIC ELECTRIC ELEMENTS

Wilbur C. Catabay

Person

Patents Grantslast 30 patents

Dielectric barrier layer for increasing electromigration lifetimes...

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Dielectric barrier layer for increasing electromigration lifetimes...

Forming copper interconnects with Sn coatings

Methods and structure for forming copper barrier layers integral wi...

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Dielectric barrier films for use as copper barrier layers in semico...

Multi-step process for forming a barrier film for use in copper lay...

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Electro chemical mechanical polishing method and device for planari...

Dielectric barrier layer for increasing electromigration lifetimes...

Interconnect dielectric tuning

Multi-step process for forming a barrier film for use in copper lay...

Planarization with reduced dishing

Interconnect dielectric tuning

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Planarization with reduced dishing

Dielectric barrier films for use as copper barrier layers in semico...

Viscous electropolishing system

Plasma treatment of low dielectric constant dielectric material to...

Ultra low dielectric constant thin film

Forming copper interconnects with Sn coatings

Process for planarizing upper surface of damascene wiring structure...

Via and metal line interface capable of reducing the incidence of e...

Electro chemical mechanical polishing method

Dual layer barrier film techniques to prevent resist poisoning

Low k dielectric composite layer for integrated circuit structure w...

Integrated circuit structure having low dielectric constant materia...

Patents Applicationslast 30 patents

DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES...

BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CUR...

CARBON NANOTUBE MEMORY CELLS HAVING FLAT BOTTOM ELECTRODE CONTACT S...

COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATI...

DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICO...

DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES...

MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAY...

Planarization with reduced dishing

Carbon nanotube memory cells having flat bottom electrode contact s...

Dual layer barrier film techniques to prevent resist poisoning

Incorporating dopants to enhance the dielectric properties of metal...

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Planarization with reduced dishing

Interconnection capacitance reduction

Interconnect dielectric tuning

Method for improved local planarity control during electropolishing

Dielectric barrier films for use as copper barrier layers in semico...

Ultra low dielectric constant thin film

Incorporating dopants to enhance the dielectric properties of metal...

ULTRA LOW DIELECTRIC CONSTANT THIN FILM

Via and metal line interface capable of reducing the incidence of e...

Dual layer barrier film techniques to prevent resist poisoning

Planarization with reduced dishing

Interconnect integration

Multi-step process for forming a barrier film for use in copper lay...

Process for planarizing upper surface of damascene wiring structure...

Plasma treatment of low dielectric constant dielectric material to...

Substrate processing system

Diamond barrier layer

Barrier and seed layer system