William D. Farwell

Person

Thousand Oaks, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Means of control for reconfigurable computers
- Patent number 9,081,901
- Issue date Jul 14, 2015
- Raytheon Company
- Lloyd J. Lewins
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Digital circuits with adaptive resistance to single event upset
- Patent number 8,278,979
- Issue date Oct 2, 2012
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital circuits with adaptive resistance to single event upset
- Patent number 8,040,157
- Issue date Oct 18, 2011
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital circuits with adaptive resistance to single event upset
- Patent number 7,795,927
- Issue date Sep 14, 2010
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for minimizing upsets in digital microcircuits vi...
- Patent number 6,948,080
- Issue date Sep 20, 2005
- Raytheon Company
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable processor with alternately interconnected arithmetic...
- Patent number 6,920,545
- Issue date Jul 19, 2005
- Raytheon Company
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable bandwidth allocation between send and receive in a dup...
- Patent number 6,775,248
- Issue date Aug 10, 2004
- Raytheon Company
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for alignment of multiple asynchronous data sources
- Patent number 6,671,754
- Issue date Dec 30, 2003
- Raytheon Company
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed technology microcircuits
- Patent number 6,667,519
- Issue date Dec 23, 2003
- Raytheon Company
- William D. Farwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Means for testing dynamic integrated circuits
- Patent number 6,324,664
- Issue date Nov 27, 2001
- Raytheon Company
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
Error correction of system transfer function by use of input compen...
- Patent number 6,038,518
- Issue date Mar 14, 2000
- Hughes Electronics Corporation
- William D. Farwell
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Preheating device for electronic circuits
- Patent number 5,896,259
- Issue date Apr 20, 1999
- Raytheon Company
- William D. Farwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Frequency independent clock synchronizer
- Patent number 5,870,445
- Issue date Feb 9, 1999
- Raytheon Company
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controllable precision on-chip delay element
- Patent number 5,731,726
- Issue date Mar 24, 1998
- Hughes Electronics
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan testing digital logic with differing frequencies of system clo...
- Patent number 5,717,702
- Issue date Feb 10, 1998
- Hughes Electronics
- Robert L. Stokes
- G01 - MEASURING TESTING
Information Patent Grant
Test for hold time margins in digital systems
- Patent number 5,708,380
- Issue date Jan 13, 1998
- Hughes Electronics
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Series connection of multiple digital devices to a single power source
- Patent number 5,703,790
- Issue date Dec 30, 1997
- Hughes Electronics
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit to improve the transient response of step-down DC to DC con...
- Patent number 5,670,865
- Issue date Sep 23, 1997
- Hughes Electronics
- William D. Farwell
- G05 - CONTROLLING REGULATING
Information Patent Grant
Contactless testing of inputs and outputs of integrated circuits
- Patent number 5,642,364
- Issue date Jun 24, 1997
- Hughes Electronics
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
Method of applying boundary test patterns
- Patent number 5,606,565
- Issue date Feb 25, 1997
- Hughes Electronics
- Christopher L. Edler
- G01 - MEASURING TESTING
Information Patent Grant
Sample and hold flip-flop for CMOS logic
- Patent number 5,576,645
- Issue date Nov 19, 1996
- Hughes Aircraft Company
- William D. Farwell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing the interconnection between logic devices
- Patent number 5,563,507
- Issue date Oct 8, 1996
- Hughes Aircraft Company
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
Boundary test cell with self masking capability
- Patent number 5,528,610
- Issue date Jun 18, 1996
- Hughes Aircraft Company
- Christopher L. Edler
- G01 - MEASURING TESTING
Information Patent Grant
Method of testing the output propagation delay of digital devices
- Patent number 5,488,309
- Issue date Jan 30, 1996
- Hughes Aircraft Company
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
High impedance technique for testing interconnections in digital sy...
- Patent number 5,473,617
- Issue date Dec 5, 1995
- Hughes Aircraft Company
- William D. Farwell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing the electrical parameters of inputs and outputs...
- Patent number 5,457,381
- Issue date Oct 10, 1995
- Hughes Aircraft Company
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
Pseudo-random vector generated testable counter
- Patent number 5,412,580
- Issue date May 2, 1995
- Hughes Aircraft Company
- James L. Fulcomer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for continuously measuring delay margins in digital systems
- Patent number 5,396,183
- Issue date Mar 7, 1995
- Hughes Aircraft Company
- William D. Farwell
- G01 - MEASURING TESTING
Information Patent Grant
Programmable hold-off for integrated circuit I/O pins
- Patent number 5,384,494
- Issue date Jan 24, 1995
- Hughes Aircraft Company
- Bradley S. Henson
- G01 - MEASURING TESTING
Information Patent Grant
Method of cancelling offset errors in phase detectors
- Patent number 5,351,000
- Issue date Sep 27, 1994
- Hughes Aircraft Company
- William D. Farwell
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL CIRCUITS WITH ADAPTIVE RESISTANCE TO SINGLE EVENT UPSET
- Publication number 20110057700
- Publication date Mar 10, 2011
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL CIRCUITS WITH ADAPTIVE RESISTANCE TO SINGLE EVENT UPSET
- Publication number 20110057692
- Publication date Mar 10, 2011
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Means of control for reconfigurable computers
- Publication number 20090113083
- Publication date Apr 30, 2009
- Lloyd J. Lewins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital circuits with adaptive resistance to single event upset
- Publication number 20090045834
- Publication date Feb 19, 2009
- Raytheon Company
- William D. Farwell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for minimizing upsets in digital microcircuits
- Publication number 20040078660
- Publication date Apr 22, 2004
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable processor architectures
- Publication number 20030135710
- Publication date Jul 17, 2003
- William D. Farwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mixed technology microcircuits
- Publication number 20030015761
- Publication date Jan 23, 2003
- William D. Farwell
- H01 - BASIC ELECTRIC ELEMENTS

William D. Farwell

Person

Patents Grantslast 30 patents

Means of control for reconfigurable computers

Digital circuits with adaptive resistance to single event upset

Digital circuits with adaptive resistance to single event upset

Digital circuits with adaptive resistance to single event upset

System and method for minimizing upsets in digital microcircuits vi...

Reconfigurable processor with alternately interconnected arithmetic...

Programmable bandwidth allocation between send and receive in a dup...

Techniques for alignment of multiple asynchronous data sources

Mixed technology microcircuits

Means for testing dynamic integrated circuits

Error correction of system transfer function by use of input compen...

Preheating device for electronic circuits

Frequency independent clock synchronizer

Controllable precision on-chip delay element

Scan testing digital logic with differing frequencies of system clo...

Test for hold time margins in digital systems

Series connection of multiple digital devices to a single power source

Circuit to improve the transient response of step-down DC to DC con...

Contactless testing of inputs and outputs of integrated circuits

Method of applying boundary test patterns

Sample and hold flip-flop for CMOS logic

Method of testing the interconnection between logic devices

Boundary test cell with self masking capability

Method of testing the output propagation delay of digital devices

High impedance technique for testing interconnections in digital sy...

Method for testing the electrical parameters of inputs and outputs...

Pseudo-random vector generated testable counter

Method for continuously measuring delay margins in digital systems

Programmable hold-off for integrated circuit I/O pins

Method of cancelling offset errors in phase detectors

Patents Applicationslast 30 patents

DIGITAL CIRCUITS WITH ADAPTIVE RESISTANCE TO SINGLE EVENT UPSET

DIGITAL CIRCUITS WITH ADAPTIVE RESISTANCE TO SINGLE EVENT UPSET

Means of control for reconfigurable computers

Digital circuits with adaptive resistance to single event upset

System and method for minimizing upsets in digital microcircuits

Reconfigurable processor architectures

Mixed technology microcircuits