William Loh

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Row based analog standard cell layout design and methodology
- Patent number 9,292,644
- Issue date Mar 22, 2016
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology for preventing functional failure caused by CDM ESD
- Patent number 9,239,896
- Issue date Jan 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-loss transmission line TDM communication link and system
- Patent number 9,087,157
- Issue date Jul 21, 2015
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit simulation using step response analysis in the frequency do...
- Patent number 8,798,981
- Issue date Aug 5, 2014
- LSI Corporation
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package having increased resistance to electrostatic...
- Patent number 8,258,016
- Issue date Sep 4, 2012
- LSI Corporation
- Choshu Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for speculative signal equalization
- Patent number 8,121,186
- Issue date Feb 21, 2012
- LSI Corporation
- Erik Chmelar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for synchronous, retimed analog to digital conv...
- Patent number 7,973,692
- Issue date Jul 5, 2011
- LSI Corporation
- Erik Chmelar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for synchronous, retimed analog to digital conv...
- Patent number 7,956,790
- Issue date Jun 7, 2011
- LSI Corporation
- Erik Chmelar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection circuit employing a micro electr...
- Patent number 7,944,655
- Issue date May 17, 2011
- LSI Corporation
- Tze Wee Chen
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Circuit protection system
- Patent number 7,777,996
- Issue date Aug 17, 2010
- LSI Corporation
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for pipelined analog to digital conversion
- Patent number 7,656,340
- Issue date Feb 2, 2010
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge series protection
- Patent number 7,551,414
- Issue date Jun 23, 2009
- LSI Corporation
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having increased resistance to electrostatic...
- Patent number 7,498,664
- Issue date Mar 3, 2009
- LSI Corporation
- Choshu Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CDM ESD event protection in application circuits
- Patent number 7,493,576
- Issue date Feb 17, 2009
- LSI Corporation
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CDM ESD event simulation and remediation thereof in application cir...
- Patent number 7,458,044
- Issue date Nov 25, 2008
- LSI Corporation
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias for electrostatic discharge protection
- Patent number 7,379,281
- Issue date May 27, 2008
- LSI Logic Corporation
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge testing
- Patent number 7,375,543
- Issue date May 20, 2008
- LSI Corporation
- Choshu Ito
- G01 - MEASURING TESTING
Information Patent Grant
Method for calculating frequency-dependent impedance in an integrat...
- Patent number 7,332,917
- Issue date Feb 19, 2008
- LSI Logic Corporation
- Kenneth J. Doniger
- G01 - MEASURING TESTING
Information Patent Grant
Energy recycling in clock distribution networks using on-chip induc...
- Patent number 7,082,580
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect routing using parallel lines and method of manufacture
- Patent number 7,014,957
- Issue date Mar 21, 2006
- LSI Logic Corporation
- Paymen Zarkesh-Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design methodology for dummy lines
- Patent number 6,961,915
- Issue date Nov 1, 2005
- LSI Logic Corporation
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mold flow regulating dam ring
- Patent number 5,964,030
- Issue date Oct 12, 1999
- VLSI Technology, Inc.
- Sang S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making electrically and thermally enhanced integrated-cir...
- Patent number 5,448,825
- Issue date Sep 12, 1995
- VLSI Technology, Inc.
- Sang S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically and thermally enhanced integrated-circuit package
- Patent number 5,331,511
- Issue date Jul 19, 1994
- VLSI Technology, Inc.
- Sang S. Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Digital Voltmeter
- Publication number 20190072589
- Publication date Mar 7, 2019
- Invecas, Inc.
- William Loh
- G01 - MEASURING TESTING
Information Patent Application
Row Based Analog Standard Cell Layout Design and Methodology
- Publication number 20130042216
- Publication date Feb 14, 2013
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-loss Transmission Line TDM Communication Link and System
- Publication number 20120224613
- Publication date Sep 6, 2012
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Synchronous, Retimed Analog to Digital Conv...
- Publication number 20100195776
- Publication date Aug 5, 2010
- Erik Chmelar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Synchronous, Retimed Analog to Digital Conv...
- Publication number 20100194616
- Publication date Aug 5, 2010
- Erik Chmelar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD
- Publication number 20100100859
- Publication date Apr 22, 2010
- LSI Corporation
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Simulation Using Step Response Analysis in the Frequency Do...
- Publication number 20090319251
- Publication date Dec 24, 2009
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION
- Publication number 20090303093
- Publication date Dec 10, 2009
- LSI CORPORATION
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Speculative Signal Equalization
- Publication number 20090304066
- Publication date Dec 10, 2009
- LSI CORPORATION
- Erik Chmelar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Electrostatic Discharge Protection Circuit Employing a Micro Electr...
- Publication number 20090296292
- Publication date Dec 3, 2009
- Tze Wee Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC...
- Publication number 20090104735
- Publication date Apr 23, 2009
- LSI Logic Corporation
- Choshu Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrostatic discharge series protection
- Publication number 20070138973
- Publication date Jun 21, 2007
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package having increased resistance to electrostatic...
- Publication number 20070132083
- Publication date Jun 14, 2007
- LSI Logic Corporation
- Choshu Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bias for electrostatic discharge protection
- Publication number 20070121262
- Publication date May 31, 2007
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrostatic discharge testing
- Publication number 20070018670
- Publication date Jan 25, 2007
- Choshu Ito
- G01 - MEASURING TESTING
Information Patent Application
Circuit protection system
- Publication number 20070019345
- Publication date Jan 25, 2007
- William M. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CDM ESD event protection in application circuits
- Publication number 20060245126
- Publication date Nov 2, 2006
- LSI Logic Corporation
- William Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CDM ESD event simulation and remediation thereof in application cir...
- Publication number 20060245127
- Publication date Nov 2, 2006
- LSI Logic Corporation
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for calculating frequency-dependent impedance in an integrat...
- Publication number 20060061373
- Publication date Mar 23, 2006
- Kenneth J. Doniger
- G01 - MEASURING TESTING
Information Patent Application
Field programmable platform array
- Publication number 20050166170
- Publication date Jul 28, 2005
- Payman Zarkesh-Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Energy recycling in clock distribution networks using on-chip induc...
- Publication number 20040158758
- Publication date Aug 12, 2004
- Payman Zarkesh-Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design methodology for dummy lines
- Publication number 20040088669
- Publication date May 6, 2004
- William M. Loh
- G06 - COMPUTING CALCULATING COUNTING

William Loh

Person

Patents Grantslast 30 patents

Row based analog standard cell layout design and methodology

Methodology for preventing functional failure caused by CDM ESD

Low-loss transmission line TDM communication link and system

Circuit simulation using step response analysis in the frequency do...

Semiconductor package having increased resistance to electrostatic...

Systems and methods for speculative signal equalization

Systems and methods for synchronous, retimed analog to digital conv...

Systems and methods for synchronous, retimed analog to digital conv...

Electrostatic discharge protection circuit employing a micro electr...

Circuit protection system

Systems and methods for pipelined analog to digital conversion

Electrostatic discharge series protection

Semiconductor package having increased resistance to electrostatic...

CDM ESD event protection in application circuits

CDM ESD event simulation and remediation thereof in application cir...

Bias for electrostatic discharge protection

Electrostatic discharge testing

Method for calculating frequency-dependent impedance in an integrat...

Energy recycling in clock distribution networks using on-chip induc...

Interconnect routing using parallel lines and method of manufacture

Design methodology for dummy lines

Mold flow regulating dam ring

Method of making electrically and thermally enhanced integrated-cir...

Electrically and thermally enhanced integrated-circuit package

Patents Applicationslast 30 patents

Digital Voltmeter

Row Based Analog Standard Cell Layout Design and Methodology

Low-loss Transmission Line TDM Communication Link and System

Systems and Methods for Synchronous, Retimed Analog to Digital Conv...

Systems and Methods for Synchronous, Retimed Analog to Digital Conv...

DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD

Circuit Simulation Using Step Response Analysis in the Frequency Do...

SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION

Systems and Methods for Speculative Signal Equalization

Electrostatic Discharge Protection Circuit Employing a Micro Electr...

SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC...

Electrostatic discharge series protection

Semiconductor package having increased resistance to electrostatic...

Bias for electrostatic discharge protection

Electrostatic discharge testing

Circuit protection system

CDM ESD event protection in application circuits

CDM ESD event simulation and remediation thereof in application cir...

Method for calculating frequency-dependent impedance in an integrat...

Field programmable platform array

Energy recycling in clock distribution networks using on-chip induc...

Design methodology for dummy lines