William Thomas Lynch

Person

Summit, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Planar isolation technique for integrated circuits
- Patent number 5,373,180
- Issue date Dec 13, 1994
- AT&T Corp.
- Steven J. Hillenius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective epitaxy of silicon in silicon dioxide apertures with supp...
- Patent number 5,304,834
- Issue date Apr 19, 1994
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective epitaxy of silicon in silicon dioxide apertures with supp...
- Patent number 5,212,112
- Issue date May 18, 1993
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices having shallow junctions
- Patent number 5,063,422
- Issue date Nov 5, 1991
- AT&T Bell Laboratories
- Steven J. Hillenius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of integrated circuit electrodes
- Patent number 5,057,455
- Issue date Oct 15, 1991
- AT&T Bell Laboratories
- Pang-Dow Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Radiation-sensitive device
- Patent number 4,996,576
- Issue date Feb 26, 1991
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned registration marks for integrated circuit fabrication
- Patent number 4,992,394
- Issue date Feb 12, 1991
- AT&T Bell Laboratories
- Robert L. Kostelak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor devices which include sources...
- Patent number 4,914,500
- Issue date Apr 3, 1990
- AT&T Bell Laboratories
- Ruichen Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laterally marching interconnecting lines in semiconductor intergrat...
- Patent number 4,914,502
- Issue date Apr 3, 1990
- AT&T Bell Laboratories
- Joseph Lebowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuit for measuring specific contact resistivity of self-ali...
- Patent number 4,896,108
- Issue date Jan 23, 1990
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- William T. Lynch
- G01 - MEASURING TESTING
Information Patent Grant
Process for manufacturing semiconductor BICMOS device
- Patent number 4,824,796
- Issue date Apr 25, 1989
- American Telephone and Telegraph Company
- Tzu-Yin Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Radiation hardened semiconductor devices
- Patent number 4,825,278
- Issue date Apr 25, 1989
- American Telephone and Telegraph Company AT&T Bell Laboratories
- Steven J. Hillenius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of FETs with source and drain contacts aligned with the...
- Patent number 4,822,754
- Issue date Apr 18, 1989
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making high-performance dram arrays including trench capa...
- Patent number 4,794,091
- Issue date Dec 27, 1988
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating latchup-preventing CMOS device
- Patent number 4,766,090
- Issue date Aug 23, 1988
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Gerald A. Coquin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making high-performance trench capacitors for DRAM cells
- Patent number 4,694,561
- Issue date Sep 22, 1987
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Joseph Lebowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky-barrier MOS devices
- Patent number 4,665,414
- Issue date May 12, 1987
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Conrad J. Koeneke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating CMOS devices
- Patent number 4,656,730
- Issue date Apr 14, 1987
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latchup-preventing CMOS device
- Patent number 4,647,957
- Issue date Mar 3, 1987
- AT&T Bell Laboratories
- Gerald A. Coquin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latchup-preventing CMOS device
- Patent number 4,646,123
- Issue date Feb 24, 1987
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming thick dielectric at the bottoms of trenches utilized in int...
- Patent number 4,643,804
- Issue date Feb 17, 1987
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of FETs
- Patent number 4,514,893
- Issue date May 7, 1985
- AT&T Bell Laboratories
- Eliezer Kinsbron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of schottky-barrier MOS FETs
- Patent number 4,485,550
- Issue date Dec 4, 1984
- AT&T Bell Laboratories
- Conrad J. Koeneke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an insulated gate field effect transistor...
- Patent number 4,471,524
- Issue date Sep 18, 1984
- AT&T Bell Laboratories
- Eliezer Kinsbron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of FETs
- Patent number 4,453,306
- Issue date Jun 12, 1984
- AT&T Bell Laboratories
- William T. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of sidewall oxide layers by reactive oxygen ion etching t...
- Patent number 4,432,132
- Issue date Feb 21, 1984
- Bell Telephone Laboratories, Incorporated
- Eliezer Kinsbron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic precharge circuitry
- Patent number 4,091,360
- Issue date May 23, 1978
- Bell Telephone Laboratories, Incorporated
- William Thomas Lynch
- G11 - INFORMATION STORAGE

William Thomas Lynch

Person

Patents Grantslast 30 patents

Planar isolation technique for integrated circuits

Selective epitaxy of silicon in silicon dioxide apertures with supp...

Selective epitaxy of silicon in silicon dioxide apertures with supp...

Devices having shallow junctions

Formation of integrated circuit electrodes

Radiation-sensitive device

Self aligned registration marks for integrated circuit fabrication

Method for fabricating semiconductor devices which include sources...

Laterally marching interconnecting lines in semiconductor intergrat...

Test circuit for measuring specific contact resistivity of self-ali...

Process for manufacturing semiconductor BICMOS device

Radiation hardened semiconductor devices

Fabrication of FETs with source and drain contacts aligned with the...

Method of making high-performance dram arrays including trench capa...

Methods for fabricating latchup-preventing CMOS device

Method of making high-performance trench capacitors for DRAM cells

Schottky-barrier MOS devices

Method for fabricating CMOS devices

Latchup-preventing CMOS device

Latchup-preventing CMOS device

Forming thick dielectric at the bottoms of trenches utilized in int...

Fabrication of FETs

Fabrication of schottky-barrier MOS FETs

Method for manufacturing an insulated gate field effect transistor...

Fabrication of FETs

Formation of sidewall oxide layers by reactive oxygen ion etching t...

Dynamic precharge circuitry