William W. Walker

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performing static timing analysis in the presence of instance-based...
- Patent number 9,355,207
- Issue date May 31, 2016
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock multiplication and distribution
- Patent number 9,348,358
- Issue date May 24, 2016
- Fujitsu Limited
- William W. Walker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for clock network meta-synthesis
- Patent number 9,280,628
- Issue date Mar 8, 2016
- Fujitsu Limited
- William Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monolithic signal generation for injection locking
- Patent number 9,270,289
- Issue date Feb 23, 2016
- Fujitsu Limited
- William W. Walker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital duty cycle correction
- Patent number 9,236,853
- Issue date Jan 12, 2016
- Fujitsu Limited
- William W. Walker
- G01 - MEASURING TESTING
Information Patent Grant
Generating behavioral models for analog circuits
- Patent number 8,903,698
- Issue date Dec 2, 2014
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crossbar switch calibration system for facilitating analog-to-digit...
- Patent number 8,878,713
- Issue date Nov 4, 2014
- Fujitsu Limited
- Pradip Thachile
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Direct mm-wave m-ary quadrature amplitude modulation (QAM) modulato...
- Patent number 8,861,627
- Issue date Oct 14, 2014
- Fujitsu Limited
- Sorin P. Voinigescu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock and data recovery (CDR) using phase interpolation
- Patent number 8,718,217
- Issue date May 6, 2014
- Fujitsu Limited
- William W. Walker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential-write, random-read memory
- Patent number 8,659,973
- Issue date Feb 25, 2014
- Fujitsu Limited
- Scott McLeod
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency synthesizer tuning
- Patent number 8,618,840
- Issue date Dec 31, 2013
- Fujitsu Limited
- William W. Walker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Baseball strike zone detection radar
- Patent number 8,591,356
- Issue date Nov 26, 2013
- Fujitsu Limited
- William Walker
- A63 - SPORTS GAMES AMUSEMENTS
Information Patent Grant
Transition-based macro-models for analog simulation
- Patent number 8,527,257
- Issue date Sep 3, 2013
- Fujitsu Limited
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Algorithmic matching of a deskew channel
- Patent number 8,432,995
- Issue date Apr 30, 2013
- Fujitsu Limited
- Samir Parikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Parallel generation and matching of a deskew channel
- Patent number 8,411,782
- Issue date Apr 2, 2013
- Fujitsu Limited
- Samir Parikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock and data recovery with a data aligner
- Patent number 8,300,754
- Issue date Oct 30, 2012
- Fujitsu Limited
- Nikola Nedovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Triple loop clock and data recovery (CDR)
- Patent number 8,300,753
- Issue date Oct 30, 2012
- Fujitsu Limited
- Nikola Nedovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Constructing a replica-based clock tree
- Patent number 8,255,196
- Issue date Aug 28, 2012
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric phase detector
- Patent number 8,138,798
- Issue date Mar 20, 2012
- Fujitsu Limited
- Nikola Nedovic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single loop frequency and phase detection
- Patent number 8,090,064
- Issue date Jan 3, 2012
- Fujitsu Limited
- Hirotaka Tamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generating multiple clock phases
- Patent number 8,058,914
- Issue date Nov 15, 2011
- Fujitsu Limited
- H. Anders Kristensson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Estimating jitter in a clock tree of a circuit and synthesizing a j...
- Patent number 7,890,904
- Issue date Feb 15, 2011
- Fujitsu Limited
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Border-enhanced sliding window scheme (SWS) for determining clock t...
- Patent number 7,788,613
- Issue date Aug 31, 2010
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sliding window scheme (SWS) for determining clock timing in a mesh-...
- Patent number 7,725,852
- Issue date May 25, 2010
- Fujitsu Limited
- Hongyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and apparatus for aperture time improvement
- Patent number 7,629,817
- Issue date Dec 8, 2009
- Fujitsu Limited
- Nikola Nedovic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electronic oscillators having a plurality of phased outputs and suc...
- Patent number 7,616,070
- Issue date Nov 10, 2009
- Fujitsu Limited
- Nestor Tzartzanis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for transmitting signals across integrated circ...
- Patent number 7,405,593
- Issue date Jul 29, 2008
- Fujitsu Limited
- Nestor Tzartzanis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electronic oscillators having a plurality of phased outputs and suc...
- Patent number 7,307,483
- Issue date Dec 11, 2007
- Fujitsu Limited
- Nestor Tzartzanis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Keeper circuits having dynamic leakage compensation
- Patent number 7,256,621
- Issue date Aug 14, 2007
- Fujitsu Limited
- Yolin Lih
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential current-mode sensing methods and apparatuses for memories
- Patent number 7,075,842
- Issue date Jul 11, 2006
- Fujitsu Limited
- Nestor Tzartzanis
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF INSTANCE-BASED...
- Publication number 20150356227
- Publication date Dec 10, 2015
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MULTIPLICATION AND DISTRIBUTION
- Publication number 20150301557
- Publication date Oct 22, 2015
- Fujitsu Limited
- William W. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MONOLITHIC SIGNAL GENERATION FOR INJECTION LOCKING
- Publication number 20150229316
- Publication date Aug 13, 2015
- Fujitsu Limited
- William W. WALKER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL DUTY CYCLE CORRECTION
- Publication number 20150222254
- Publication date Aug 6, 2015
- Fujitsu Limited
- William W. WALKER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FREQUENCY SYNTHESIZER TUNING
- Publication number 20140015569
- Publication date Jan 16, 2014
- Fujitsu Limited
- William W. WALKER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GENERATING BEHAVIORAL MODELS FOR ANALOG CIRCUITS
- Publication number 20130311152
- Publication date Nov 21, 2013
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CLOCK NETWORK META-SYNTHESIS
- Publication number 20130055186
- Publication date Feb 28, 2013
- FUJITSU LIMITED
- William Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSITION-BASED MACRO-MODELS FOR ANALOG SIMULATION
- Publication number 20130006595
- Publication date Jan 3, 2013
- FUJITSU LIMITED
- Subodh M. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric Phase Detector
- Publication number 20120177162
- Publication date Jul 12, 2012
- FUJITSU LIMITED
- Nikola Nedovic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BASEBALL STRIKE ZONE DETECTION RADAR
- Publication number 20120146291
- Publication date Jun 14, 2012
- FUJITSU LIMITED
- William Walker
- A63 - SPORTS GAMES AMUSEMENTS
Information Patent Application
ALGORITHMIC MATCHING OF A DESKEW CHANNEL
- Publication number 20120023380
- Publication date Jan 26, 2012
- FUJITSU LIMITED
- Samir Parikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEQUENTIAL-WRITE, RANDOM-READ MEMORY
- Publication number 20110310692
- Publication date Dec 22, 2011
- FUJITSU LIMITED
- Scott McLeod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MM-WAVE M-ARY QUADRATURE AMPLITUDE MODULATION (QAM) MODULATO...
- Publication number 20110013726
- Publication date Jan 20, 2011
- FUJITSU LIMITED
- Sorin P. Voinigescu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock and Data Recovery with a Data Aligner
- Publication number 20100104057
- Publication date Apr 29, 2010
- Fujitsu Limited
- Nikola Nedovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Symmetric Phase Detector
- Publication number 20100090723
- Publication date Apr 15, 2010
- Fujitsu Limited
- Nikola Nedovic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Generating Multiple Clock Phases
- Publication number 20100090733
- Publication date Apr 15, 2010
- Fujitsu Limited
- H. Anders Kristensson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Triple Loop Clock and Data Recovery (CDR)
- Publication number 20100091925
- Publication date Apr 15, 2010
- Fujitsu Limited
- Nikola Nedovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock and Data Recovery (CDR) Using Phase Interpolation
- Publication number 20100091927
- Publication date Apr 15, 2010
- Fujitsu Limited
- William W. Walker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Frequency Detector
- Publication number 20100085086
- Publication date Apr 8, 2010
- Fujitsu Limited
- Nikola Nedovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Parallel Generation and Matching of a Deskew Channel
- Publication number 20100086075
- Publication date Apr 8, 2010
- Fujitsu Limited
- Samir Parikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Constructing a Replica-Based Clock Tree
- Publication number 20100049481
- Publication date Feb 25, 2010
- Fujitsu Limited
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Apparatus for Aperature Time Improvement
- Publication number 20080191770
- Publication date Aug 14, 2008
- Fujitsu Limited
- Nikola Nedovic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Single Loop Frequency and Phase Detection
- Publication number 20080192873
- Publication date Aug 14, 2008
- Fujitsu Limited
- Hirotaka Tamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Electronic Oscillators Having a Plurality of Phased Outputs and Suc...
- Publication number 20080061896
- Publication date Mar 13, 2008
- Fujitsu Limited
- Nestor Tzartzanis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electronic oscillators having a plurality of phased outputs and suc...
- Publication number 20070182497
- Publication date Aug 9, 2007
- Nestor Tzartzanis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and methods for transmitting signals across integrated circ...
- Publication number 20070103199
- Publication date May 10, 2007
- Nestor Tzartzanis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Border-Enhanced Sliding Window Scheme (SWS) for Determining Clock T...
- Publication number 20070038430
- Publication date Feb 15, 2007
- William W. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-...
- Publication number 20070016882
- Publication date Jan 18, 2007
- Hongyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Estimating Jitter In A Clock Tree Of A Circuit And Synthesizing A J...
- Publication number 20060288320
- Publication date Dec 21, 2006
- Rajeev Murgai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Keeper circuits having dynamic leakage compensation
- Publication number 20060214695
- Publication date Sep 28, 2006
- Yolin Lih
- H03 - BASIC ELECTRONIC CIRCUITRY

William W. Walker

Person

Patents Grantslast 30 patents

Performing static timing analysis in the presence of instance-based...

Clock multiplication and distribution

System and method for clock network meta-synthesis

Monolithic signal generation for injection locking

Digital duty cycle correction

Generating behavioral models for analog circuits

Crossbar switch calibration system for facilitating analog-to-digit...

Direct mm-wave m-ary quadrature amplitude modulation (QAM) modulato...

Clock and data recovery (CDR) using phase interpolation

Sequential-write, random-read memory

Frequency synthesizer tuning

Baseball strike zone detection radar

Transition-based macro-models for analog simulation

Algorithmic matching of a deskew channel

Parallel generation and matching of a deskew channel

Clock and data recovery with a data aligner

Triple loop clock and data recovery (CDR)

Constructing a replica-based clock tree

Symmetric phase detector

Single loop frequency and phase detection

Generating multiple clock phases

Estimating jitter in a clock tree of a circuit and synthesizing a j...

Border-enhanced sliding window scheme (SWS) for determining clock t...

Sliding window scheme (SWS) for determining clock timing in a mesh-...

System and apparatus for aperture time improvement

Electronic oscillators having a plurality of phased outputs and suc...

Systems and methods for transmitting signals across integrated circ...

Electronic oscillators having a plurality of phased outputs and suc...

Keeper circuits having dynamic leakage compensation

Differential current-mode sensing methods and apparatuses for memories

Patents Applicationslast 30 patents

PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF INSTANCE-BASED...

CLOCK MULTIPLICATION AND DISTRIBUTION

MONOLITHIC SIGNAL GENERATION FOR INJECTION LOCKING

DIGITAL DUTY CYCLE CORRECTION

FREQUENCY SYNTHESIZER TUNING

GENERATING BEHAVIORAL MODELS FOR ANALOG CIRCUITS

SYSTEM AND METHOD FOR CLOCK NETWORK META-SYNTHESIS

TRANSITION-BASED MACRO-MODELS FOR ANALOG SIMULATION

Symmetric Phase Detector

BASEBALL STRIKE ZONE DETECTION RADAR

ALGORITHMIC MATCHING OF A DESKEW CHANNEL

SEQUENTIAL-WRITE, RANDOM-READ MEMORY

DIRECT MM-WAVE M-ARY QUADRATURE AMPLITUDE MODULATION (QAM) MODULATO...

Clock and Data Recovery with a Data Aligner

Symmetric Phase Detector

Generating Multiple Clock Phases

Triple Loop Clock and Data Recovery (CDR)

Clock and Data Recovery (CDR) Using Phase Interpolation

Digital Frequency Detector

Parallel Generation and Matching of a Deskew Channel

Constructing a Replica-Based Clock Tree

System and Apparatus for Aperature Time Improvement

Single Loop Frequency and Phase Detection

Electronic Oscillators Having a Plurality of Phased Outputs and Suc...

Electronic oscillators having a plurality of phased outputs and suc...

Systems and methods for transmitting signals across integrated circ...

Border-Enhanced Sliding Window Scheme (SWS) for Determining Clock T...

Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-...

Estimating Jitter In A Clock Tree Of A Circuit And Synthesizing A J...

Keeper circuits having dynamic leakage compensation