William Wai Yan Ho

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Using barycenter compact model to determine IR drop for circuit net...
- Patent number 12,159,093
- Issue date Dec 3, 2024
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Barycenter compact model to determine IR drop exact solution for ci...
- Patent number 11,847,397
- Issue date Dec 19, 2023
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a barycenter compact model for a circuit network
- Patent number 11,574,105
- Issue date Feb 7, 2023
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a Barycenter compact model for a circuit network
- Patent number 10,885,255
- Issue date Jan 5, 2021
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning a system graph for circuit simulation to obtain an exa...
- Patent number 10,558,772
- Issue date Feb 11, 2020
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a Barycenter compact model for a circuit network
- Patent number 10,366,195
- Issue date Jul 30, 2019
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning electronic circuits for simulation on multiple processors
- Patent number 10,140,396
- Issue date Nov 27, 2018
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating integrated circuit simulation results
- Patent number 10,068,043
- Issue date Sep 4, 2018
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical visualization-based analysis of integrated circuits
- Patent number 9,984,195
- Issue date May 29, 2018
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving a circuit network in multicore or distributed computing env...
- Patent number 9,471,733
- Issue date Oct 18, 2016
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating integrated circuit simulation results
- Patent number 9,454,637
- Issue date Sep 27, 2016
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical visualization-based analysis of integrated circuits
- Patent number 9,286,430
- Issue date Mar 15, 2016
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning electronic circuits for simulation on multicore proces...
- Patent number 9,218,441
- Issue date Dec 22, 2015
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving a circuit network in hierarchical, multicore, and distribut...
- Patent number 9,129,079
- Issue date Sep 8, 2015
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating integrated circuit simulation results
- Patent number 9,122,837
- Issue date Sep 1, 2015
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving a hierarchical circuit network using a barycenter compact m...
- Patent number 9,111,058
- Issue date Aug 18, 2015
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning electronic circuits for simulation on multicore proces...
- Patent number 8,903,686
- Issue date Dec 2, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network tearing for circuit simulation
- Patent number 8,818,786
- Issue date Aug 26, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving a circuit network in hierarchical, multicore, and distribut...
- Patent number 8,738,335
- Issue date May 27, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating integrated circuit simulation results
- Patent number 8,719,760
- Issue date May 6, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving a hierarchical circuit network using a Barycenter compact m...
- Patent number 8,694,302
- Issue date Apr 8, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical visualization-based analysis of integrated circuits
- Patent number 8,667,455
- Issue date Mar 4, 2014
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network tearing for circuit simulation
- Patent number 8,554,532
- Issue date Oct 8, 2013
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling and simulating the impact of imperfectly patterned via arr...
- Patent number 8,468,482
- Issue date Jun 18, 2013
- Worldwide Pro Ltd.
- Robert C. Pack
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Hierarchical variation analysis of integrated circuits
- Patent number 8,453,102
- Issue date May 28, 2013
- Worldwide Pro Ltd.
- Robert C. Pack
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Using multiple processors to simulate electronic circuits
- Patent number 8,396,696
- Issue date Mar 12, 2013
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connectivity-based approach for extracting layout parasitics
- Patent number 6,438,729
- Issue date Aug 20, 2002
- Synopsys, Inc.
- William Wai-Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of extracting layout parasitics for nets of an integrated ci...
- Patent number 6,421,814
- Issue date Jul 16, 2002
- Synopsys, Inc.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer-based rule checking for an integrated circuit layout
- Patent number 6,378,110
- Issue date Apr 23, 2002
- Synopsys, Inc.
- William Wai-Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of extracting layout parasitics for nets of an integrated ci...
- Patent number 6,128,768
- Issue date Oct 3, 2000
- Synopsys, Inc.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Using a Barycenter Compact Model for a Circuit Network
- Publication number 20160048625
- Publication date Feb 18, 2016
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING

William Wai Yan Ho

Person

Patents Grantslast 30 patents

Using barycenter compact model to determine IR drop for circuit net...

Barycenter compact model to determine IR drop exact solution for ci...

Using a barycenter compact model for a circuit network

Using a Barycenter compact model for a circuit network

Partitioning a system graph for circuit simulation to obtain an exa...

Using a Barycenter compact model for a circuit network

Partitioning electronic circuits for simulation on multiple processors

Validating integrated circuit simulation results

Hierarchical visualization-based analysis of integrated circuits

Solving a circuit network in multicore or distributed computing env...

Validating integrated circuit simulation results

Hierarchical visualization-based analysis of integrated circuits

Partitioning electronic circuits for simulation on multicore proces...

Solving a circuit network in hierarchical, multicore, and distribut...

Validating integrated circuit simulation results

Solving a hierarchical circuit network using a barycenter compact m...

Partitioning electronic circuits for simulation on multicore proces...

Network tearing for circuit simulation

Solving a circuit network in hierarchical, multicore, and distribut...

Validating integrated circuit simulation results

Solving a hierarchical circuit network using a Barycenter compact m...

Hierarchical visualization-based analysis of integrated circuits

Network tearing for circuit simulation

Modeling and simulating the impact of imperfectly patterned via arr...

Hierarchical variation analysis of integrated circuits

Using multiple processors to simulate electronic circuits

Connectivity-based approach for extracting layout parasitics

Method of extracting layout parasitics for nets of an integrated ci...

Layer-based rule checking for an integrated circuit layout

Method of extracting layout parasitics for nets of an integrated ci...

Patents Applicationslast 30 patents

Using a Barycenter Compact Model for a Circuit Network