Xiaochun Tan

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Chip package structure and method of making the same
- Patent number 8,294,256
- Issue date Oct 23, 2012
- Hangzhou Silergy Semiconductor Technology Ltd
- Wei Chen
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor devices with conductive clips
- Patent number 8,288,200
- Issue date Oct 16, 2012
- Diodes Inc.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin quad flat package with no leads (QFN) fabrication methods
- Patent number 8,008,128
- Issue date Aug 30, 2011
- Shanghai Kaihong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly process
- Patent number 7,960,209
- Issue date Jun 14, 2011
- Diodes, Inc.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor power device
- Patent number 7,834,433
- Issue date Nov 16, 2010
- Shanghai Kaihong Technology Co., Ltd.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with multiple heat sinks
- Patent number 7,786,555
- Issue date Aug 31, 2010
- Diodes, Incorporated
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip scale package fabrication methods
- Patent number 7,745,261
- Issue date Jun 29, 2010
- Shanghai Kaihong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin quad flat package with no leads (QFN) fabrication methods
- Patent number 7,713,784
- Issue date May 11, 2010
- Shanghai Kaihong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip scale package (CSP) assembly apparatus and method
- Patent number 7,682,874
- Issue date Mar 23, 2010
- Shanghai KaiHong Technology Co., Ltd
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonded chip scale package fabrication methods
- Patent number 7,517,726
- Issue date Apr 14, 2009
- Shanghai KaiHong Technology Co., Ltd
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Quad flat no-lead (QFN) chip package assembly apparatus and method
- Patent number 7,402,459
- Issue date Jul 22, 2008
- Shanghai Kaihong Technology Co., Ltd.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with interlocking clip
- Patent number 7,264,999
- Issue date Sep 4, 2007
- Diodes, Inc.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with interlocking clip
- Patent number 7,095,113
- Issue date Aug 22, 2006
- Diodes Incorporated
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME
- Publication number 20120313219
- Publication date Dec 13, 2012
- Hangzhou Silergy Semiconductor Technology LTD
- Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS
- Publication number 20110281398
- Publication date Nov 17, 2011
- SHANGHAI KAIHONG TECHNOLOGY CO., LTD
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip package structure and method of making the same
- Publication number 20110254143
- Publication date Oct 20, 2011
- Hangzhou Silergy Semiconductor Technology LTD
- Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin Quad Flat Package with No Leads (QFN) Fabrication Methods
- Publication number 20100178733
- Publication date Jul 15, 2010
- Shanghai KaiHong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS
- Publication number 20090233401
- Publication date Sep 17, 2009
- Shanghai KaiHong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip Scale Package Fabrication Methods
- Publication number 20090215227
- Publication date Aug 27, 2009
- Shanghai KaiHong Technology Co., Ltd.
- Xiaochun Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor power device
- Publication number 20080164590
- Publication date Jul 10, 2008
- Diodes, Inc.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip scale package (CSP) assembly apparatus and method
- Publication number 20080014677
- Publication date Jan 17, 2008
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Quad flat no-lead (QFN) chip package assembly apparatus and method
- Publication number 20080009103
- Publication date Jan 10, 2008
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices with conductive clips
- Publication number 20070123073
- Publication date May 31, 2007
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices with multiple heat sinks
- Publication number 20070090463
- Publication date Apr 26, 2007
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with interlocking clip
- Publication number 20060214290
- Publication date Sep 28, 2006
- Diodes, Inc.
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with interlocking clip
- Publication number 20050199985
- Publication date Sep 15, 2005
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device assembly process
- Publication number 20050189658
- Publication date Sep 1, 2005
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device support structures
- Publication number 20050189626
- Publication date Sep 1, 2005
- Tan Xiaochun
- H01 - BASIC ELECTRIC ELEMENTS

Xiaochun Tan

Person

Patents Grantslast 30 patents

Chip package structure and method of making the same

Semiconductor devices with conductive clips

Thin quad flat package with no leads (QFN) fabrication methods

Semiconductor device assembly process

Semiconductor power device

Semiconductor devices with multiple heat sinks

Chip scale package fabrication methods

Thin quad flat package with no leads (QFN) fabrication methods

Chip scale package (CSP) assembly apparatus and method

Wire bonded chip scale package fabrication methods

Quad flat no-lead (QFN) chip package assembly apparatus and method

Semiconductor device with interlocking clip

Semiconductor device with interlocking clip

Patents Applicationslast 30 patents

CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME

THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS

Chip package structure and method of making the same

Thin Quad Flat Package with No Leads (QFN) Fabrication Methods

THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS

Chip Scale Package Fabrication Methods

Semiconductor power device

Chip scale package (CSP) assembly apparatus and method

Quad flat no-lead (QFN) chip package assembly apparatus and method

Semiconductor devices with conductive clips

Semiconductor devices with multiple heat sinks

Semiconductor device with interlocking clip

Semiconductor device with interlocking clip

Semiconductor device assembly process

Semiconductor device support structures