Yanbin Luo

Person

Portland, OR, US

People

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH BACKSIDE ISOLATON REGION
- Publication number 20250212470
- Publication date Jun 26, 2025
- Intel Corporation
- Feng Zhang
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH SEMICONDUCTOR STRUCTURE EXTENDING AC...
- Publication number 20250203975
- Publication date Jun 19, 2025
- Guowei Xu
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH TRANSISTOR GATE-CHANNEL ARRANGEM...
- Publication number 20250194070
- Publication date Jun 12, 2025
- Tao Chu
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES
- Publication number 20250169130
- Publication date May 22, 2025
- Intel Corporation
- Tao Chu
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
- Publication number 20250140649
- Publication date May 1, 2025
- Intel Corporation
- Feng Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Publication number 20250112120
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS
- Publication number 20250113586
- Publication date Apr 3, 2025
- Intel Corporation
- Rahul PANDEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...
- Publication number 20250113595
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Publication number 20250107175
- Publication date Mar 27, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...
- Publication number 20250006734
- Publication date Jan 2, 2025
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT
- Publication number 20240321887
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT
- Publication number 20240321859
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT
- Publication number 20240113118
- Publication date Apr 4, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH PROTECTION LINER BETWEEN DOPED SEMI...
- Publication number 20240105718
- Publication date Mar 28, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION
- Publication number 20240088217
- Publication date Mar 14, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS
- Publication number 20240088292
- Publication date Mar 14, 2024
- Intel Corporation
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DEVICE WITH BACKSIDE ISOLATON REGION

INTEGRATED CIRCUIT DEVICE WITH SEMICONDUCTOR STRUCTURE EXTENDING AC...

INTEGRATED CIRCUIT STRUCTURES WITH TRANSISTOR GATE-CHANNEL ARRANGEM...

INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES

INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING

NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS

MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS

PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...

INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT

INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT

ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT

INTEGRATED CIRCUIT DEVICES WITH PROTECTION LINER BETWEEN DOPED SEMI...

BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION

FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS