Patent Application
20240105718
For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each contact becomes increasingly significant. Careful design of transistors may help with such an optimization.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
The fabrication of IC devices may include various steps. In some instances, there may be a need to electrically isolate two doped semiconductor regions in a channel material as part of a fabrication process in forming an IC device. To that end, a portion of the channel material may be removed to create an opening between two doped semiconductor regions, for example, using any suitable etching techniques, and subsequently an insulating material may be used to fill the opening to provide electrical isolation between the doped semiconductor regions. Unfortunately, the etching can damage the surface of one or both of the doped semiconductor regions. For instance, etching can unintentionally remove a portion from the sidewalls of one or both of the doped semiconductor regions. The damage to the doped semiconductor region(s) can lower the performance of the device.
In the context of fabricating transistors, such as P-type metal-oxide-semiconductor (PMOS) transistors and/or N-type metal-oxide-semiconductor (NMOS) transistors, the doped semiconductor regions may correspond to the source and/or drain (S/D) regions of the transistors. In some examples, an IC device may have multiple transistors formed adjacent to one another, where the source region of one of a nearest-neighbor pair of transistors may be adjacent to the drain region of the other one of the nearest-neighbor pair of transistors. To electrically isolate the two neighboring transistors, a portion of the channel material between the source region of one of the nearest-neighbor pair of transistors and the drain region of the other one of the nearest-neighbor pair of transistors may be removed, for example, by etching. The etching can cause damage to the source region of the transistor and/or the drain region of the adjacent transistor. In some instances, the damage to the S/D regions can impact the threshold voltages of the transistors (e.g., VTN in the case of a NMOS transistor or VTP in the case of a PMOS transistor). The threshold voltage of an NMOS transistor or a PMOS transistor may refer to the minimum gate-to-source voltage that is needed to create a conducting path between the source and drain terminals of the transistor. Additionally or alternatively, the damage to the S/D regions can degrade the saturation current (ISSAT) of the transistors. The saturation current of a transistor may refer to the maximum amount of current that can flow through the transistor. Accordingly, damages to S/D regions of a transistor can impact the transistor performance.
To address the performance impact discussed above, the present disclosure provides techniques for fabricating IC devices with isolation between two doped semiconductor regions in a way that can avoid damage to the doped semiconductor regions. For example, the two doped semiconductor regions may extend into a portion of a channel material, and a portion of the channel material between the two doped semiconductor regions may be removed by performing etching in multiple steps and depositing a protection liner during the etching process. More specifically, the protection liner can be deposited between two etching steps or prior to an etching step that is likely to cause damage to the doped semiconductor regions.
According to embodiments of the present disclosure, an IC device may include a channel material having a first face and a second face, where the second face may be opposite to the first face. The IC device may further include a first doped region and a second doped region in the channel material. The first and second doped regions may include doped semiconductor materials. Each of the first and second doped regions may extend from the second face of the channel material towards the first face of the channel material. For example, at least one of the first or second doped regions may extend from the second face towards the first face by a first distance. The IC device may further include an insulator structure in a portion of the channel material between the first and second doped regions. The insulator structure may extend from the second face of the channel material towards the first face of the channel material by a second distance, where the second distance may be greater than the first distance. In some instances, the insulator structure can extend through the entire thickness of the channel material, and thus the second distance may correspond a distance between the first and second faces of the channel material. Further, the insulator structure may have a first portion and a second portion, where the first portion may be a portion of the insulator structure extending from the second face of the channel material to the first distance, and the second portion may be a portion of the insulator structure extending from the first distance to the second distance. The insulator structure may include a liner material on at least portions of sidewalls of the insulator structure in the first portion but may not be on at least portions of the sidewalls of the insulator structure in the second portion.
In some embodiments, the insulator structure may include an insulator material. The insulator material may be on a portion of a sidewall of the insulator structure that is closest to the first doped region, where the liner material is between the insulator material and the first doped region. The insulator material may also be on a portion of a sidewall of the insulator structure that is closest to the second doped region, where the liner material is between the insulator material and the second doped region. Further, on the portion of the sidewall of the insulator structure that is closest to the first doped region, the liner material may be in contact with the first doped region. In a similar way, on the portion of the sidewall of the insulator structure that is closest to the second doped region, the liner material may be in contact with the second doped region.
In some embodiments, the insulator material in at least a portion of the second portion of the insulator structure may be in contact with the channel material. In some embodiments, a width of a sub-portion (e.g., a first sub-portion) of the second portion of the insulator structure may be smaller than a width of another sub-portion (e.g., a second sub-portion) of the second portion of the insulator structure. The width of the first sub-portion and the width of the second sub-portion may be in a dimension measured in a direction substantially parallel to a support over which the IC device is provided. In some embodiments, an average width of the first portion of the insulator structure is greater than an average width of the second portion of the insulator structure.
In some embodiments, the liner material may be in a layer (e.g., a thin film) having a thickness between about 0.5 and 2.5 nanometers. In some embodiments, the liner material may be selective with respect to the channel material. In some embodiments, the liner material may include oxygen. In some embodiments, the channel material may have a shape of a fin. In general, the channel material may have any suitable shapes (e.g., in the shape of a plane, a nanoribbon, a nanowire, etc.).
In some embodiments, the IC device may further include a first transistor and a second transistor adjacent to the first transistor, where the first doped region may be a source region of the first transistor and the second doped region may be a drain region of the second transistor. In some embodiments, the IC device may have a third doped region and a fourth doped region in the channel material, where the first, second, third, and fourth doped regions may be spaced apart from each other, the first and second doped regions may be a nearest-neighbor pair of doped regions in the channel material, and at least a portion of the channel material channel material has a shape of a fin.
The present disclosure may use the terms “protection liner,” “liner,” “protection material,” and “liner material” interchangeably to refer to a strong, tough material (e.g., in a thin layer) that can protect doped semiconductor regions from damage during an etching process.
Each of the structures, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which being solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “sidewall” may refer to a surface that is designed to be perpendicular to a support structure (e.g., a die, a wafer, a substrate, a package substrate, or a carrier substrate) of the IC device but may not always end up being exactly perpendicular due to manufacturing processes used to fabricate IC devices. Therefore, as used herein, the term “sidewall” refers to a surface that extends away from a support structure of the IC device and that may be substantially perpendicular, within a certain tolerance. In another example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. Similarly, the terms naming various compounds refer to materials having any combination of the individual elements within a compound (e.g., “gallium arsenide” or “GaAs” may refer to a material that includes Gallium and Arsenic). Further, the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10% of a target value based on the context of a particular value as described herein or as known in the art.
The term “interconnect” may refer to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The terms such as “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described to be “on” a second layer refers to a layer that is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. In the drawings, same reference numerals refer to the same or analogous elements/materials shown so that, unless stated otherwise, explanations of an element/material with a given reference numeral provided in context of one of the drawings are applicable to other drawings where element/materials with the same reference numerals may be illustrated.
In the drawings, some schematic illustrations of example structures of various structures, devices, and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices with a protection liner between doped semiconductor regions as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various IC devices with a protection liner between doped semiconductor regions as described herein may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, transmitters, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital, or may include a combination of analog and digital circuitry, and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC devices with a protection liner between doped semiconductor regions as described herein may be included in a RFIC, which may, e.g., be included in any component associated with an IC of an RF receiver, an RF transmitter, or an RF transceiver, or any other RF device, e.g., as used in telecommunications within base stations (BS) or user equipment (UE) devices. Such components may include, but are not limited to, power amplifiers, RF switches, RF filters (including arrays of RF filters, or RF filter banks), or impedance tuners. In some embodiments, the IC devices with a protection liner between doped semiconductor regions as described herein may be employed as part of a chipset for executing one or more related functions in a computer.
Although the operations of the method 100 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, an IC device with a protection liner between doped semiconductor regions to protect the doped semiconductor regions from damage during an etching process as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more protection liners are deposited to protect the doped semiconductor regions from damage during an etching process as described herein will be included.
In addition, the example manufacturing method 100 may include other operations not specifically shown in
Various operations of the method 100 may be illustrated with reference to the example embodiments shown in
A number of elements referred to in the description of
Turning to
Implementations of the present disclosure may be formed or carried out on any suitable support structure, such as a substrate, a die, a wafer, or a chip. The support structure may, e.g., be the wafer 2000 of
Further, in general, the channel material 202 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material 202 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the channel material 202 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material 202 may have a thickness between about 5 and 30 nanometers, including all values and ranges therein. Further, in general, the channel material 202 may have any suitable shapes, for example, a fin, a nanowire, a nanoribbon, a plane, etc.
The method 100 may further include a process 104, which may include providing doped semiconductor regions in the channel material. An IC structure 300, depicted in
In the illustrated example of
In general, the doped semiconductor regions 205 may be formed at the process 104 using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the channel material 202 to form the doped semiconductor regions 205. An annealing process that activates the dopants and causes them to diffuse further into the channel material 202 may follow the ion implantation process. In the latter process, a portion of the channel material 202 may first be etched to form a recess at the location of the future doped semiconductor region 205. An epitaxial deposition process may then be carried out to fill the recess with material that is used to fabricate the doped semiconductor regions 205. In some implementations, the doped semiconductor regions 205 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the doped semiconductor regions 205 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the doped semiconductor regions 205.
As further shown in
As further shown in
In general, the insulator material 210 may be provided at the process 104 using a technique such as spin-coating, dip-coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition). In some embodiments, the insulator material 210 may be provided over the doped semiconductor regions 205, an opening may be created in the insulator material 210, and the contacts 206 may be formed in the opening of the insulator material 210, for example, by depositing one or more electrically conductive materials along sidewalls of the opening, followed by silicide annealing and a contact metal fill with an electrically conductive material. The electrically conductive material may be as discussed above.
As further shown in
The method 100 may further include a process 106, which may include removing a portion of the channel material to create an opening between a nearest-neighbor pair of two of the doped semiconductor regions. An IC structure 400, depicted in
In some embodiments, the opening 401 may be created in the process 106 using any suitable etching technique (e.g., a dry etch, such as e.g., radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE) in combination with lithography (e.g., photolithography or electron-beam lithography) to define the locations and the sizes of these openings. In some embodiments, the etches performed in the process 106 to form the opening 401 may include an anisotropic etch, using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. An etch is described as “anisotropic” if etchants remove the material preferentially in one direction and not in all directions. In some embodiments, during the etches of the process 106, the IC structure 400 may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.
The method 100 may further include a process 108, which may include depositing a protection material (or a liner material) along sidewalls and a bottom of the opening created in the process 106. For example, the protection material may be conformally deposited over and in the opening. An IC structure 500, depicted in
While
In some embodiments, the liner material 212 may be in a layer (e.g., a thin film) having a thickness 502 between about 0.5 and 2.5 nanometers (e.g., between about 1 and 2 nanometers or about 1.5 nanometers). In some examples, the thickness of the layer of liner material 212 may be substantially uniform along the sidewall 504 and the bottom 506 of the opening 401.
In some embodiments, the liner material 212 may include an oxide material (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). In some embodiments, the liner material 212 may be etch-selective with respect to the channel material 202. Stated differently, when etchants used to etch the channel material 202 at a subsequent process 108 may not substantially etch the liner material 212, enabling selective etching of the channel material 202 but not the liner material 212. In general, the liner material 212 may be a strong and tough material that can be used to form a thin film to protect the doped semiconductor regions 205b and 205c from damage caused by etching, for example, at the subsequent process 108.
In general, the liner material 212 be deposited at the process 108 using CVD, PVD, ALD, any other suitable processes, and/or combinations thereof. In certain examples, the liner material 212 may be deposited at the process 108 using ALD.
The method 100 may further include a process 110, which may include removing at least a portion of the protection material at the bottom of the opening to expose a portion of the channel material. An IC structure 600, depicted in
The method 100 may further include a process 112, which may include removing a portion of the channel material to extend the opening through the channel material. In some instances, the method 100 may or may not include the process 110. In any case, the process 112 may extend the opening (created at the process 106) beyond the protection material (deposited at the process 108) to form the extended opening. An IC structure 700, depicted in
The method 100 may further include a process 114, which may include depositing an insulator material in the extended opening. For instance, the insulator material may fill the lined opening and at least some portions of the cut region (e.g., the cut region 702) in the channel material. In other words, the extended opening may at least partially be filled with the insulator material. An IC structure 800, depicted in
Further, the insulator structure 810 may have a first portion 810-1, a second portion 810-2, and a third portion 810-3. The first portion 810-1 may be a portion of the insulator structure 810 that extends from the second face 203 of the channel material 202 to about the first distance 301. The second portion 810-2 may be a portion of the insulator structure 810 that extends from about the first distance 301 to the second distance 801. The third portion 810-3 may be a portion of the insulator structure 810 that extends away from the channel material 202.
As further shown in
As further shown in
In some embodiments, the insulator material 214 in at least a portion of the second portion 810-2 of the insulator structure 810 may be in contact with the channel material 202. As discussed above with reference to the process 110, the opening 702 in the channel material 202 may have varying widths. Accordingly, in some embodiments, a width (e.g., shown by 803) of a sub-portion (e.g., a first sub-portion) of the second portion 810-2 of the insulator structure 810 may be smaller than a width (e.g., shown by 805) of another sub-portion (e.g., a second sub-portion) of the second portion 810-2 of the insulator structure 810. The width 803 of the first sub-portion and the width 805 of the second sub-portion may be in a dimension measured in a direction substantially parallel to a support over which the IC device is provided. As further shown, an average width of the first portion 810-1 of the insulator structure is greater than an average width of the second portion 810-2 of the insulator structure 810.
In general, the insulator material 214 may be any suitable dielectric material as discussed above with reference to the insulator material 210. In some embodiments, the insulator material 214 may have the same composition of material(s) as the insulator material 210. In other embodiments, the insulator material 214 may have different composition of material(s) than the insulator material 210. Further, the insulator material deposited at the process 112 may be performed using any suitable techniques, such as, but not limited to, ALD, CVD, PVD, PECVD.
While
As discussed above, in some instances, the channel material 202 may be in the shape of a fin, and thus the process 112 in which a portion of the channel material 202 is removed to extend the opening 401 through the channel material 202 may be referred to as a fin trim isolation (FTI) process.
As shown in
In various embodiments, the semiconductor material of the nanoribbon 908 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the nanoribbon 908 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 908 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 908 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 908 may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
The IC device 900 may further include a gate dielectric 904 and a gate electrode 906 between the doped semiconductor regions 205a and 205b and between the doped semiconductor regions 205c and 205d. For instance, the gate dielectric 904 and a gate electrode 906 may be part of the gate structure 208 discussed above with reference to
The gate dielectric 904 may include one or more high-k dielectric materials and may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 904 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 904 during manufacture of the IC device 900 to improve the quality of the gate dielectric 904. In some embodiments, the gate dielectric 904 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers.
In some embodiments, the gate dielectric 904 may be a multilayer gate dielectric, e.g., it may include any of the high-k dielectric materials in one layer and a layer of IGZO. In some embodiments, the gate stack (i.e., a combination of the gate dielectric 904 and the gate electrode 906) may be arranged so that the IGZO is disposed between the high-k dielectric and the channel material 202. In such embodiments, the IGZO may be in contact with the channel material 202 and may provide the interface between the channel material 202 and the remainder of the multilayer gate dielectric 904. The IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10).
The gate electrode 906 may include at least one P-type work function metal or N-type work function metal, depending on whether the S/D electrodes 326 are to be included in a PMOS transistor or an NMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode 906 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode 906 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 906 may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a barrier layer.
The IC device 900 may further include an insulator material 902 that surrounds the gate stack (the gate dielectric 904 and the gate electrode 906). In general, the insulator material 902 may be any suitable dielectric material as discussed above with reference to the insulator material 210. In some embodiments, the insulator material 902 may have the same composition of material(s) as the insulator material 210 and/or the insulator material 214. In other embodiments, the insulator material 902 may have different composition of material(s) than the insulator material 210 and/or 214.
In some embodiments, an IC device implemented using the method 100 discussed above with reference to
In some embodiments of the IC device, the protection material may be in a layer having a thickness 502 between about 0.5 and 2.5 nanometers (e.g., between about 1 and 2 nanometers or about 1.5 nanometers). In some embodiment, the protection material may include at least one of aluminum and oxygen (e.g., aluminum oxide) or hafnium and oxygen (e.g., hafnium oxide). In some embodiments, the IC device may further include a first doped semiconductor region and a second doped semiconductor region at least partially in the semiconductor material. The first and second doped semiconductor regions may extend from the second face of the semiconductor material towards the first face of the semiconductor material by the first distance. In some instances, the first doped semiconductor region may correspond respectively to the doped semiconductor region 205b and the second doped semiconductor region may correspond to the doped semiconductor region 205c. In some embodiments, the insulator material may be on a portion of a sidewall of the insulator structure closest to the first doped region, and the protection material may be between the insulator material and the first doped region. Further, the insulator material may be on a portion of a sidewall of the insulator structure that is closest to the second doped region, and the protection material is between the insulator material and the second doped region. In some embodiments of the IC device, the IC device may further include a stack of nanoribbons (e.g., the nanoribbons 908) extending, along an axis about parallel to the first face, between the first doped semiconductor region and the second doped semiconductor region. The stack of nanoribbons may include a second semiconductor material (e.g., the same as or different than the first semiconductor material).
IC devices with a protection liner between doped semiconductor regions as disclosed herein may be included in any suitable electronic device.
As shown in
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC device having at least one nearest-neighboring pairs of doped semiconductor regions with a protection liner therebetween, e.g., any of the IC devices shown in
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC devices implementing at least one nearest-neighboring pairs of doped semiconductor regions with a protection liner therebetween as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
In various embodiments, IC devices with at least one nearest-neighboring pair of doped semiconductor regions with a protection liner therebetween as described herein may be particularly advantageous for use within the one or more communication chips 2412, described above. For example, such IC devices with at least one nearest-neighboring pair of doped semiconductor regions with a protection liner therebetween may be used to implement one or more of power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, upconverters, downconverters, and duplexers, e.g., as a part of implementing an RF transmitter, an RF receiver, or an RF transceiver.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
In general, the RF device 2500 may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz). In some embodiments, the RF device 2500 may be used for wireless communications, e.g., in a BS or a UE device of any suitable cellular wireless communications technology, such as GSM, WCDMA, or LTE. In a further example, the RF device 2500 may be used as, or in, e.g., a BS or a UE device of a mm-wave wireless technology such as fifth generation (5G) wireless (i.e., high frequency/short wavelength spectrum, e.g., with frequencies in the range between about 20 and 60 GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF device 2500 may be used for wireless communications using WiFi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm, or a frequency band of 5.8 GHz, spectrum, corresponding to a wavelength of about 5 cm), e.g., in a WiFi-enabled device such as a desktop, a laptop, a video game console, a smart phone, a tablet, a smart TV, a digital audio player, a car, a printer, etc. In some implementations, a WiFi-enabled device may, e.g., be a node in a smart system configured to communicate data with other nodes, e.g., a smart sensor. Still in another example, the RF device 2500 may be used for wireless communications using Bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device 2500 may be used for transmitting and/or receiving RF signals for purposes other than communication, e.g., in an automotive radar system, or in medical applications such as magneto-resonance imaging (MRI).
In various embodiments, the RF device 2500 may be included in frequency division duplexing (FDD) or time-domain duplex (TDD) variants of frequency allocations that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE devices to a BS) and the downlink (i.e., RF signals transmitted from the BS to the US devices) may use separate frequency bands at the same time. In a TDD system, the uplink and the downlink may use the same frequencies but at different times.
A number of components are illustrated in
In some embodiments, some or all of the components included in the RF device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, e.g., on a single SoC die.
Additionally, in various embodiments, the RF device 2500 may not include one or more of the components illustrated in
As shown in
The antenna 2502 may be configured to wirelessly transmit and/or receive RF signals in accordance with any wireless standards or protocols, e.g., Wi-Fi, LTE, or GSM, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. If the RF device 2500 is an FDD transceiver, the antenna 2502 may be configured for concurrent reception and transmission of communication signals in separate, i.e., non-overlapping and non-continuous, bands of frequencies, e.g., in bands having a separation of, e.g., 20 MHz from one another. If the RF device 2500 is a TDD transceiver, the antenna 2502 may be configured for sequential reception and transmission of communication signals in bands of frequencies which may be the same, or overlapping for TX and RX paths. In some embodiments, the RF device 2500 may be a multi-band RF device, in which case the antenna 2502 may be configured for concurrent reception of signals having multiple RF components in separate frequency bands and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2502 may be a single wide-band antenna or a plurality of band-specific antennas (i.e., a plurality of antennas each configured to receive and/or transmit signals in a specific band of frequencies). In various embodiments, the antenna 2502 may include a plurality of antenna elements, e.g., a plurality of antenna elements forming a phased antenna array (i.e., a communication system or an array of antennas that may use a plurality of antenna elements and phase shifting to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array may offer advantages such as increased gain, ability of directional steering, and simultaneous communication. In some embodiments, the RF device 2500 may include more than one antenna 2502 to implement antenna diversity. In some such embodiments, the RF switch 2534 may be deployed to switch between different antennas.
An output of the antenna 2502 may be coupled to the input of the duplexer 2504. The duplexer 2504 may be any suitable component configured for filtering multiple signals to allow for bidirectional communication over a single path between the duplexer 2504 and the antenna 2502. The duplexer 2504 may be configured for providing RX signals to the RX path of the RF device 2500 and for receiving TX signals from the TX path of the RF device 2500.
The RF device 2500 may include one or more local oscillators 2506, configured to provide local oscillator signals which may be used for downconversion of the RF signals received by the antenna 2502 and/or upconversion of the signals to be transmitted by the antenna 2502.
The RF device 2500 may include the digital processing unit 2508, which may include one or more processing devices. In some embodiments, the digital processing unit 2508 may be implemented as the processing device 2402 shown in
Turning to the details of the RX path that may be included in the RF device 2500, the RX path amplifier 2512 may include an low-noise amplifier (LNA). An input of the RX path amplifier 2512 may be coupled to an antenna port (not shown) of the antenna 2502, e.g., via the duplexer 2504. The RX path amplifier 2512 may amplify the RF signals received by the antenna 2502.
An output of the RX path amplifier 2512 may be coupled to an input of the RX path pre-mix filter 2514, which may be, e.g., a harmonic or band-pass filter, configured to filter received RF signals that have been amplified by the RX path amplifier 2512.
An output of the RX path pre-mix filter 2514 may be coupled to an input of the RX path mixer 2516, also referred to as a downconverter. The RX path mixer 2516 may include two inputs and one output. A first input may be configured to receive the RX signals, which may be current signals, indicative of the signals received by the antenna 2502 (e.g., the first input may receive the output of the RX path pre-mix filter 2514). A second input may be configured to receive local oscillator signals from one of the local oscillators 2506. The RX path mixer 2516 may then mix the signals received at its two inputs to generate a downconverted RX signal, provided at an output of the RX path mixer 2516. As used herein, downconversion refers to a process of mixing a received RF signal with a local oscillator signal to generate a signal of a lower frequency. In particular, the downconverter 2516 may be configured to generate the sum and/or the difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2500 may implement a direct-conversion receiver (DCR), also known as homodyne, synchrodyne, or zero-IF receiver, in which case the RX path mixer 2516 may be configured to demodulate the incoming radio signals using local oscillator signals whose frequency is identical to, or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2500 may make use of downconversion to an intermediate frequency (IF). IFs may be used in superheterodyne radio receivers, in which a received RF signal is shifted to an IF, before the final detection of the information in the received signal is done. Conversion to an IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and to tune. In some embodiments, the RX path mixer 2516 may include several such stages of IF conversion.
Although a single RX path mixer 2516 is shown in the RX path of
The output of the RX path mixer 2516 may, optionally, be coupled to the RX path post-mix filter 2518, which may be low-pass filters. In case the RX path mixer 2516 is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively may be coupled to respective individual first and second RX path post-mix filters included in the filter 2518.
The ADC 2520 may be configured to convert the mixed RX signals from the RX path mixer 2516 from analog to digital domain. The ADC 2520 may be a quadrature ADC that, similar to the RX path quadrature mixer 2516, may include two ADCs, configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC 2520 may be provided to the digital processing unit 2508, configured to perform various functions related to digital processing of the RX signals so that information encoded in the RX signals can be extracted.
Turning to the details of the TX path that may be included in the RF device 2500, the digital signal to later be transmitted (TX signal) by the antenna 2502 may be provided, from the digital processing unit 2508, to the DAC 2530. Similar to the ADC 2520, the DAC 2530 may include two DACs, configured to convert, respectively, digital I- and Q-path TX signal components to analog form.
Optionally, the output of the DAC 2530 may be coupled to the TX path pre-mix filter 2528, which may be a low-pass filter (or a pair of filters, in case of quadrature processing) configured to filter out, from the analog TX signals output by the DAC 2530, the signal components outside of the desired band. The digital TX signals may then be provided to the TX path mixer 2526, which may also be referred to as an upconverter. Similar to the RX path mixer 2516, the TX path mixer 2526 may include a pair of TX path mixers, for in-phase and quadrature component mixing. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of the TX path mixer 2526 may include two inputs and one output. A first input may receive the TX signal components, converted to the analog form by the respective DAC 2530, which are to be upconverted to generate RF signals to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2506 (in various embodiments, the local oscillator 2506 may include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for the mixer 2516 in the RX path and the mixer 2526 in the TX path). The second TX path mixer may generate a quadrature phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create a real RF signal. A second input of each of the TX path mixers may be coupled the local oscillator 2506.
Optionally, the RF device 2500 may include the TX path post-mix filter 2524, configured to filter the output of the TX path mixer 2526.
The TX path amplifier 2522 may be a power amplifier (PA), configured to amplify the upconverted RF signal before providing it to the antenna 2502 for transmission.
In various embodiments, any of the RX path pre-mix filter 2514, the RX path post-mix filter 2518, the TX post-mix filter 2524, and the TX pre-mix filter 2528 may be implemented as RF filters. In some embodiments, each of such RF filters may include one or more, typically a plurality of, resonators (e.g., film bulk acoustic resonators (FBARs), Lamb wave resonators, and/or contour-wave resonators), arranged, e.g., in a ladder configuration. An individual resonator of an RF filter may include a layer of a piezoelectric material such as aluminum nitride (AlN), enclosed between a bottom electrode and a top electrode, with a cavity provided around a portion of each electrode in order to allow a portion of the piezoelectric material to vibrate during operation of the filter. In some embodiments, an RF filter may be implemented as a plurality of RF filters, or a filter bank. A filter bank may include a plurality of RF resonators which may be coupled to a switch, e. g., the RF switch 2534, configured to selectively switch any one of the plurality of RF resonators on and off (i.e., activate any one of the plurality of RF resonators), in order to achieve desired filtering characteristics of the filter bank (i.e., in order to program the filter bank). For example, such a filter bank may be used to switch between different RF frequency ranges when the RF device 2500 is, or is included in, a BS or in a UE device. In another example, such a filter bank may be programmable to suppress TX leakage on the different duplex distances.
The impedance tuner 2532 may include any suitable circuitry, configured to match the input and output impedances of the different RF circuitries to minimize signal losses in the RF device 2500. For example, the impedance tuner 2532 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2502 may be particularly advantageous because antenna's impedance is a function of the environment that the RF device 2500 is in, e.g. antenna's impedance changes depending on, e.g., if the antenna is held in a hand, placed on a car roof, etc.
As described above, the RF switch 2534 may be used to selectively switch between a plurality of instances of any one of the components shown in
In various embodiments, IC devices including one or more nearest-neighboring pairs of doped semiconductor regions with a protection liner therebetween as described herein may be particularly advantageous when used in any of the duplexer 2504, RX path amplifier 2512, RX path pre-mix filter 2514, RX path post-mix filter 2518, TX path amplifier 2522, TX path pre-mix filter 2528, TX path post-mix filter 2524, impedance tuner 2532, and/or RF switch 2534.
The RF device 2500 provides a simplified version and, in further embodiments, other components not specifically shown in
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an integrated circuit (IC) device, including a channel material (e.g., the channel material 202) having a first face and a second face opposite the first face; a first doped semiconductor region (e.g., the doped semiconductor region 205b) and a second doped semiconductor region (e.g., the doped semiconductor region 205c) in the channel material, where at least one of the first doped semiconductor region or the second doped semiconductor region extends from the second face of the channel material towards the first face of the channel material by a first distance from the second face of the channel material; an insulator structure (e.g., the insulator structure 810) in a portion of the channel material between the first doped region and the second doped region, the insulator structure extending from the second face of the channel material towards the first face of the channel material by a second distance from the second face of the channel material, the second distance being greater than the first distance, where the insulator structure has a first portion (e.g., the first portion 810-1) and a second portion (e.g., the second portion 810-2), the first portion is a portion of the insulator structure extending from the second face of the channel material to the first distance, the second portion is a portion of the insulator structure extending from the first distance from the second face of the channel material to the second distance from the second face of the channel material, and the insulator structure includes a liner material (e.g., the liner material 212) that is present on at least portions of sidewalls of the insulator structure in the first portion but absent on at least portions of the sidewalls of the insulator structure in the second portion.
Example 2 provides the IC device according to example 1, where the second distance is substantially equal to a distance between the first face and the second face (i.e., the insulator structure extends through the entire thickness of the channel material).
Example 3 provides the IC device according to examples 1 or 2, where the insulator structure further includes an insulator material (e.g., the insulator material 214), on a portion of a sidewall of the insulator structure that is closest to the first doped region, the liner material is between the insulator material and the first doped region, and on a portion of a sidewall of the insulator structure that is closest to the second doped region, the liner material is between the insulator material and the second doped region.
Example 4 provides the IC device according to example 3, where on the portion of the sidewall of the insulator structure that is closest to the first doped region, the liner material is in contact with the first doped region.
Example 5 provides the IC device according to example 4, where on the portion of the sidewall of the insulator structure that is closest to the second doped region, the liner material is in contact with the second doped region.
Example 6 provides the IC device according to any one of examples 3-5, where the insulator material in at least a portion of the second portion of the insulator structure is in contact with the channel material.
Example 7 provides the IC device according to example 6, where a width (i.e., a dimension measured in a direction substantially parallel to a support over which the IC device is provided, the support being, e.g., a die, a wafer, a substrate, a package substrate, or a carrier substrate, e.g., a dimension along the y-axis of the coordinate system shown in the present drawings) of a sub-portion of the second portion of the insulator structure is smaller than a width of another sub-portion of the second portion of the insulator structure.
Example 8 provides the IC device according to any one of examples 1-7, where an average width of the first portion of the insulator structure is greater than an average width of the second portion of the insulator structure.
Example 9 provides the IC device according to any one of examples 1-8, where the liner material has a thickness between about 0.5 and 2.5 nanometers (e.g., between about 1 and 2 nm or about 1.5 nm).
Example 10 provides the IC device according to any one of examples 1-9, where the liner material is etch-selective with respect to the channel material.
Example 11 provides the IC device according to any one of examples 1-10, where the liner material includes oxygen.
Example 12 provides the IC device according to any one of examples 1-11, where the channel material has a shape of a fin.
Example 13 provides the IC device according to any one of examples 1-12, further including a first transistor (e.g., 208) and a second transistor (e.g., 209) (adjacent to the first transistor), where the first doped semiconductor region is a source region or a drain region of the first transistor, and the second doped semiconductor region is a source region or a drain region of the second transistor.
Example 14 provides the IC device according to any one of examples 1-13, further including a third doped region and a fourth doped region in the channel material, where the first, second, third, and fourth doped regions are spaced apart from each other, the first and second doped regions are a nearest-neighbor pair of doped regions, and at least a portion of the channel material channel material has a shape of a fin.
Example 15 provides the IC device according to any one of examples 1-14, where the liner material is absent on all portions of the sidewalls of the insulator structure in the second portion.
Example 16 provides an integrated circuit (IC) device, including a semiconductor material having a first face and a second face opposite the first face; and an insulator structure comprising a protection material and an insulator material, the insulator structure extending from the second face towards the first face, wherein a first portion of the insulator structure extends from the second face to a first distance and includes the protection material between the insulator material and the semiconductor material, a second portion of the insulator structure extends from the first distance to a second distance from the second face, the second distance being greater than the first distance, and in at least a part of the second portion, the insulator material is in contact with the semiconductor material.
Example 17 provides the IC device according to example 16, where the protection material has a thickness between about 0.5 and 2.5 nanometers (e.g., between about 1 and 2 nanometers or about 1.5 nanometers).
Example 18 provides the IC device according to any one of examples 16-17, where the protection material includes at least one of aluminum and oxygen, or hafnium and oxygen.
Example 19 provides the IC device according to any one of examples 16-18, further including a first doped semiconductor region (e.g., the doped semiconductor region 205b) and a second doped semiconductor region (e.g., the doped semiconductor region 205c) at least partially in the semiconductor material, extending from the second face of the semiconductor material towards the first face of the semiconductor material by the first distance or less.
Example 20 provides the IC device according to any one of examples 16-19, where on a portion of a sidewall of the insulator structure that is closest to the first doped region, the protection material is between the insulator material and the first doped region, and on a portion of a sidewall of the insulator structure that is closest to the second doped region, the protection material is between the insulator material and the second doped region.
Example 21 provides the IC device according to any one of examples 16-20, where the semiconductor material is a first semiconductor material, and the IC device further including one or more nanoribbons extending, along an axis about parallel to the first face, between the first doped semiconductor region and the second doped semiconductor region, the one or more nanoribbons including a second semiconductor material (e.g., the same as or different than the first semiconductor material).
Example 22 provides a method of fabricating an integrated circuit (IC) structure, the method including providing a channel material; providing a first doped semiconductor region and a second doped semiconductor region in the channel material; removing a portion of the channel material to create an opening between the first doped semiconductor region and the second doped semiconductor region; depositing a protection material along sidewalls and a bottom of the opening; after depositing the protection material, extending the opening beyond the protection material to form an extended opening; and at least partially filling the extended opening with an insulator material.
Example 23 provides the method according to example 21, further including before extending the opening, removing a portion of the protection material at the bottom of the opening to expose a portion of the channel material.
Example 24 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a central processing unit.
Example 25 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a memory device.
Example 26 provides the IC device according to any one of the preceding examples, where the IC device further includes a plurality of memory cells, each of the memory cells including a storage element.
Example 27 provides the IC device according to example 26, where the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.
Example 28 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a logic circuit.
Example 29 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of input/output circuitry.
Example 30 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a field programmable gate array transceiver.
Example 31 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a field programmable gate array logic.
Example 32 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a power delivery circuitry.
Example 33 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of a III-V amplifier.
Example 34 provides the IC device according to any one of the preceding examples, where the IC device includes or is a part of Peripheral Component Interconnect Express circuitry or Double Data Rate transfer circuitry.
Example 35 provides an IC package that includes a die including an IC device according to any one of the preceding examples; and a further IC component, coupled to the die.
Example 36 provides the IC package according to example 35, where the further IC component includes one of a package substrate, an interposer, or a further IC support structure.
Example 37 provides a computing device that includes a carrier substrate and an IC device, coupled to the carrier substrate, where the IC device is an IC device according to any one of the preceding examples, or the IC device is included in the IC package according to any one of examples 35-36.
Example 38 provides the computing device according to example 37, where the computing device is a wearable or handheld computing device.
Example 39 provides the computing device according to examples 37 or 38, where the computing device further includes one or more communication chips and an antenna.
Example 40 provides the computing device according to any one of examples 37-39, where the carrier substrate is a motherboard.
Example 41 provides a method of manufacturing an IC device, the method including providing the IC device according to any one of the preceding examples.
