Yeshik Shin

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Communications architecture for transmission of data between memory...
- Patent number 7,903,684
- Issue date Mar 8, 2011
- Silicon Image, Inc.
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for integrating packet type information with sync...
- Patent number 7,746,798
- Issue date Jun 29, 2010
- Silicon Image, Inc.
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multisection memory bank system
- Patent number 7,340,558
- Issue date Mar 4, 2008
- Silicon Image, Inc.
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory architecture with multiple serial communications ports
- Patent number 7,257,129
- Issue date Aug 14, 2007
- Silicon Image
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for nesting of communications packets
- Patent number 7,154,905
- Issue date Dec 26, 2006
- Silicon Image
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for communicating control information via out-of-...
- Patent number 7,113,507
- Issue date Sep 26, 2006
- Silicon Image
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for transition-controlled selective block inversi...
- Patent number 7,039,121
- Issue date May 2, 2006
- Silicon Image
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for host handling of communications errors
- Patent number 6,976,201
- Issue date Dec 13, 2005
- Silicon Image
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for DC-balancing at the physical layer
- Patent number 6,771,192
- Issue date Aug 3, 2004
- Silicon Image, Inc.
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
COMMUNICATIONS ARCHITECTURE FOR MEMORY-BASED DEVICES
- Publication number 20080126824
- Publication date May 29, 2008
- Silicon Image, Inc.
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for nesting of communications packets
- Publication number 20040004975
- Publication date Jan 8, 2004
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for communicating control information via out-of-...
- Publication number 20030227947
- Publication date Dec 11, 2003
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for transition-controlled selective block inversi...
- Publication number 20030210162
- Publication date Nov 13, 2003
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multisection memory bank system
- Publication number 20030208655
- Publication date Nov 6, 2003
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Communications architecture for memory-based devices
- Publication number 20020191475
- Publication date Dec 19, 2002
- Dongyun Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for dynamic segmentation of communications packets
- Publication number 20020191603
- Publication date Dec 19, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for integrating packet type information with sync...
- Publication number 20020172200
- Publication date Nov 21, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for packet ordering based on packet type
- Publication number 20020167945
- Publication date Nov 14, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for asymmetric packet ordering between communicat...
- Publication number 20020159450
- Publication date Oct 31, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for plesiosynchronous communications with null in...
- Publication number 20020159552
- Publication date Oct 31, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for host handling of communications errors
- Publication number 20020157054
- Publication date Oct 24, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Communications architecture for storage-based devices
- Publication number 20020154633
- Publication date Oct 24, 2002
- Yeshik Shin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Yeshik Shin

Person

Patents Grantslast 30 patents

Communications architecture for transmission of data between memory...

Method and system for integrating packet type information with sync...

Multisection memory bank system

Memory architecture with multiple serial communications ports

Method and system for nesting of communications packets

Method and system for communicating control information via out-of-...

Method and system for transition-controlled selective block inversi...

Method and system for host handling of communications errors

Method and system for DC-balancing at the physical layer

Patents Applicationslast 30 patents

COMMUNICATIONS ARCHITECTURE FOR MEMORY-BASED DEVICES

Method and system for nesting of communications packets

Method and system for communicating control information via out-of-...

Method and system for transition-controlled selective block inversi...

Multisection memory bank system

Communications architecture for memory-based devices

Method and system for dynamic segmentation of communications packets

Method and system for integrating packet type information with sync...

Method and system for packet ordering based on packet type

Method and system for asymmetric packet ordering between communicat...

Method and system for plesiosynchronous communications with null in...

Method and system for host handling of communications errors

Communications architecture for storage-based devices