Ying-Tsong Loh

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Antifuse structures
- Patent number 5,821,558
- Issue date Oct 13, 1998
- VLSI Technology, Inc.
- Yu-Pin Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitance measurement using an RLC circuit model
- Patent number 5,793,640
- Issue date Aug 11, 1998
- VLSI Technology, Inc.
- Koucheng Wu
- G01 - MEASURING TESTING
Information Patent Grant
Methods for fabricating anti-fuse structures
- Patent number 5,793,094
- Issue date Aug 11, 1998
- VLSI Technology, Inc.
- Ivan Sanchez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for fabricationg anti-fuse devices
- Patent number 5,789,795
- Issue date Aug 4, 1998
- VLSI Technology, Inc.
- Ivan Sanchez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making antifuse structures using implantation of both neu...
- Patent number 5,783,467
- Issue date Jul 21, 1998
- VLSI Technology, Inc.
- Yu-Pin Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure and method for determining metal-oxide-silicon field...
- Patent number 5,773,317
- Issue date Jun 30, 1998
- VLSI Technology Inc.
- Koucheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method for sub-half micron CMOS transistor
- Patent number 5,759,901
- Issue date Jun 2, 1998
- VLSI Technology, Inc.
- Ying-Tsong Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for programming antifuse structures
- Patent number 5,753,540
- Issue date May 19, 1998
- VLSI Technology, Inc.
- Koucheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing contact resistance for semiconductor manufacturi...
- Patent number 5,700,717
- Issue date Dec 23, 1997
- VLSI Technology, Inc.
- Edward D. Nowak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD and hot carrier resistant integrated circuit structure
- Patent number 5,631,485
- Issue date May 20, 1997
- VLSI Technology, Inc.
- Yi-Hen Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Large-tilted-angle nitrogen implant into dielectric regions overlay...
- Patent number 5,516,707
- Issue date May 14, 1996
- VLSI Technology, Inc.
- Ying-Tsong Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an ESD and hot carrier resistant integrated circu...
- Patent number 5,496,751
- Issue date Mar 5, 1996
- VLSI Technology, Inc.
- Yi-Hen Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for creating a self-aligned bicmos-compatible...
- Patent number 5,444,003
- Issue date Aug 22, 1995
- VLSI Technology, Inc.
- Chung S. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating auxiliary gate lightly doped drain (AGLDD) st...
- Patent number 5,411,906
- Issue date May 2, 1995
- VLSI Technology, Inc.
- Eric A. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts with gate overlapped lightly doped drain (gol...
- Patent number 5,340,761
- Issue date Aug 23, 1994
- VLSI Technology, Inc.
- Ying T. Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BICMOS-compatible method for creating a bipolar transistor with lat...
- Patent number 5,288,652
- Issue date Feb 22, 1994
- VLSI Technology, Inc.
- Chung S. Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing gate overlapped lightly doped drain (GOLDD) st...
- Patent number 5,227,320
- Issue date Jul 13, 1993
- VLSI Technology, Inc.
- Eric A. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making extended polysilicon self-aligned gate overlapped...
- Patent number 5,196,357
- Issue date Mar 23, 1993
- VLSI Technology, Inc.
- William J. Boardman
- H01 - BASIC ELECTRIC ELEMENTS

Ying-Tsong Loh

Person

Patents Grantslast 30 patents

Antifuse structures

Capacitance measurement using an RLC circuit model

Methods for fabricating anti-fuse structures

Methods and apparatus for fabricationg anti-fuse devices

Method of making antifuse structures using implantation of both neu...

Test structure and method for determining metal-oxide-silicon field...

Fabrication method for sub-half micron CMOS transistor

Apparatus and method for programming antifuse structures

Method of reducing contact resistance for semiconductor manufacturi...

ESD and hot carrier resistant integrated circuit structure

Large-tilted-angle nitrogen implant into dielectric regions overlay...

Method of forming an ESD and hot carrier resistant integrated circu...

Method and structure for creating a self-aligned bicmos-compatible...

Method of fabricating auxiliary gate lightly doped drain (AGLDD) st...

Self-aligned contacts with gate overlapped lightly doped drain (gol...

BICMOS-compatible method for creating a bipolar transistor with lat...

Method for producing gate overlapped lightly doped drain (GOLDD) st...

Method of making extended polysilicon self-aligned gate overlapped...