Yisuo LI

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Pillar-shaped semiconductor device and manufacturing method thereof
- Patent number 12,096,608
- Issue date Sep 17, 2024
- Unisantis Electronics Singapore Pte. Ltd.
- Fujio Masuoka
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Method for manufacturing three-dimensional semiconductor device
- Patent number 11,862,464
- Issue date Jan 2, 2024
- Unisantis Electronics Singapore Pte. Ltd.
- Fujio Masuoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device production method and semiconductor device
- Patent number 9,666,688
- Issue date May 30, 2017
- Unisantis Electronics Singapore Pte. Ltd.
- Fujio Masuoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device production method and semiconductor device
- Patent number 9,490,362
- Issue date Nov 8, 2016
- Unisantis Electronics Singapore Pte Ltd.
- Fujio Masuoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with double doped drain transistor
- Patent number 9,269,770
- Issue date Feb 23, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure including high voltage device
- Patent number 8,410,553
- Issue date Apr 2, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jeoung Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS using a combination of enhanced dielectric stress layer and d...
- Patent number 8,334,567
- Issue date Dec 18, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance LDMOS device having enhanced dielectric strain layer
- Patent number 8,293,614
- Issue date Oct 23, 2012
- GlobalFoundries Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance LDMOS device having enhanced dielectric strain layer
- Patent number 8,163,621
- Issue date Apr 24, 2012
- GlobalFoundries Singapore Pte. Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing an elevated drain
- Patent number 7,951,680
- Issue date May 31, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Guowei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to form source and drain regions over doped de...
- Patent number 7,888,752
- Issue date Feb 15, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- King Jien Chui
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor structure including high voltage device
- Patent number 7,867,862
- Issue date Jan 11, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jeoung Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS using a combination of enhanced dielectric stress layer and d...
- Patent number 7,824,968
- Issue date Nov 2, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device layout and channeling implant process
- Patent number 7,573,099
- Issue date Aug 11, 2009
- Chartered Semiconductor Manufacturing, Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device layout and channeling implant process
- Patent number 7,253,483
- Issue date Aug 7, 2007
- Chartered Semiconductor Manufacturing, Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method to form source and drain regions over doped de...
- Patent number 7,202,133
- Issue date Apr 10, 2007
- Chartered Semiconductor Manufacturing, Ltd.
- King Jien Chui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost source drain elevation through poly amorphizing implant te...
- Patent number 7,101,743
- Issue date Sep 5, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device layout and channeling implant process
- Patent number 6,972,236
- Issue date Dec 6, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
- Publication number 20230058135
- Publication date Feb 23, 2023
- Unisantis Electronics Singapore PTE Ltd.
- Nozomu HARADA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20220028869
- Publication date Jan 27, 2022
- Unisantis Electronics Singapore PTE Ltd.
- Fujio MASUOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Manufacturing Three-Dimensional Semiconductor Device
- Publication number 20210358754
- Publication date Nov 18, 2021
- Unisantis Electronics Singapore PTE Ltd.
- Fujio MASUOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE
- Publication number 20160380080
- Publication date Dec 29, 2016
- Unisantis Electronics Singapore PTE LTD.
- Fujio MASUOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE
- Publication number 20150287822
- Publication date Oct 8, 2015
- Unisantis Electronics Singapore PTE Ltd.
- Fujio MASUOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
- Publication number 20120119293
- Publication date May 17, 2012
- Chartered Semiconductor Manufacturing Ltd.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE
- Publication number 20110079850
- Publication date Apr 7, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jeoung Mo KOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS Using A Combination of Enhanced Dielectric Stress Layer and D...
- Publication number 20110042743
- Publication date Feb 24, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sanford CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS
- Publication number 20100109045
- Publication date May 6, 2010
- Chartered Semiconductor Manufacturing LTD.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN
- Publication number 20100109097
- Publication date May 6, 2010
- Chartered Semiconductor Manufacturing LTD.
- Guowei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
- Publication number 20090302385
- Publication date Dec 10, 2009
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE
- Publication number 20090072310
- Publication date Mar 19, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jeoung Mo KOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS using a combination of enhanced dielectric stress layer and d...
- Publication number 20080014690
- Publication date Jan 17, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH DOUBLE DOPED DRAIN TRANSISTOR
- Publication number 20070210376
- Publication date Sep 13, 2007
- Chartered Semiconductor Manufacturing LTD.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method to form source and drain regions over doped de...
- Publication number 20070178652
- Publication date Aug 2, 2007
- King Jien Chui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device layout and channeling implant process
- Publication number 20050280082
- Publication date Dec 22, 2005
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device layout and channeling implant process
- Publication number 20050236677
- Publication date Oct 27, 2005
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE LAYOUT AND CHANNELING IMPLANT PROCESS
- Publication number 20050170595
- Publication date Aug 4, 2005
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method to form source and drain regions over doped de...
- Publication number 20050156253
- Publication date Jul 21, 2005
- King Jien Chui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST SOURCE DRAIN ELEVATION THROUGH POLY AMORPHIZING IMPLANT TE...
- Publication number 20050148125
- Publication date Jul 7, 2005
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Pillar-shaped semiconductor device and manufacturing method thereof

Method for manufacturing three-dimensional semiconductor device

Semiconductor device production method and semiconductor device

Semiconductor device production method and semiconductor device

Integrated circuit system with double doped drain transistor

Semiconductor structure including high voltage device

LDMOS using a combination of enhanced dielectric stress layer and d...

High performance LDMOS device having enhanced dielectric strain layer

High performance LDMOS device having enhanced dielectric strain layer

Integrated circuit system employing an elevated drain

Structure and method to form source and drain regions over doped de...

Semiconductor structure including high voltage device

LDMOS using a combination of enhanced dielectric stress layer and d...

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

Structure and method to form source and drain regions over doped de...

Low cost source drain elevation through poly amorphizing implant te...

Semiconductor device layout and channeling implant process

Patents Applicationslast 30 patents

PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

PILLAR-SHAPED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Method For Manufacturing Three-Dimensional Semiconductor Device

SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE

HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER

SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE

LDMOS Using A Combination of Enhanced Dielectric Stress Layer and D...

INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS

INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN

HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER

SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE

LDMOS using a combination of enhanced dielectric stress layer and d...

INTEGRATED CIRCUIT SYSTEM WITH DOUBLE DOPED DRAIN TRANSISTOR

Structure and method to form source and drain regions over doped de...

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

SEMICONDUCTOR DEVICE LAYOUT AND CHANNELING IMPLANT PROCESS

Structure and method to form source and drain regions over doped de...

LOW COST SOURCE DRAIN ELEVATION THROUGH POLY AMORPHIZING IMPLANT TE...