Yong Kong Siew

Person

Selangor, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Poly profile engineering to modulate spacer induced stress for devi...
- Patent number 8,519,445
- Issue date Aug 27, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Vincent Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly profile engineering to modulate spacer induced stress for devi...
- Patent number 7,993,997
- Issue date Aug 9, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Vincent Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for corrosion prevention during planarization
- Patent number 7,947,604
- Issue date May 24, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Fan Zhang
- B24 - GRINDING POLISHING
Information Patent Grant
Interconnections for integrated circuits including reducing an over...
- Patent number 7,833,900
- Issue date Nov 16, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Lup San Leong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to eliminate contact plug sidewall slit
- Patent number 7,670,946
- Issue date Mar 2, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Yong Kong Siew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to control dual damascene trench etch profile and trench dep...
- Patent number 7,247,555
- Issue date Jul 24, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating an air gap shallow trench isolation (STI) st...
- Patent number 6,406,975
- Issue date Jun 18, 2002
- Chartered Semiconductor Manufacturing Inc.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified buried contact process for IC device fabrication
- Patent number 6,121,135
- Issue date Sep 19, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Yong Kong Siew
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVI...
- Publication number 20110266628
- Publication date Nov 3, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Vincent HO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTIONS FOR INTEGRATED CIRCUITS
- Publication number 20090233441
- Publication date Sep 17, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Lup San Leong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CORROSION PREVENTION DURING PLANARIZATION
- Publication number 20090191792
- Publication date Jul 30, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Fan ZHANG
- B24 - GRINDING POLISHING
Information Patent Application
POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVI...
- Publication number 20090085122
- Publication date Apr 2, 2009
- Vincent Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods to eliminate contact plug sidewall slit
- Publication number 20070264824
- Publication date Nov 15, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yong Kong Siew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Entire encapsulation of Cu interconnects using self-aligned CuSiN film
- Publication number 20070197023
- Publication date Aug 23, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel method to control dual damascene trench etch profile and tren...
- Publication number 20050170625
- Publication date Aug 4, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS

Yong Kong Siew

Person

Patents Grantslast 30 patents

Poly profile engineering to modulate spacer induced stress for devi...

Poly profile engineering to modulate spacer induced stress for devi...

Method for corrosion prevention during planarization

Interconnections for integrated circuits including reducing an over...

Methods to eliminate contact plug sidewall slit

Method to control dual damascene trench etch profile and trench dep...

Method for fabricating an air gap shallow trench isolation (STI) st...

Modified buried contact process for IC device fabrication

Patents Applicationslast 30 patents

POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVI...

INTERCONNECTIONS FOR INTEGRATED CIRCUITS

METHOD FOR CORROSION PREVENTION DURING PLANARIZATION

POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVI...

Methods to eliminate contact plug sidewall slit

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Novel method to control dual damascene trench etch profile and tren...